A new scalable VLSI architecture for Reed-Solomon decoders

Wilhelm, W.

doi:10.1109/4.748191

Cited by 52 publications

(5 citation statements)

References 13 publications

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“…Calculation of the Error Locator Polynomial using an algorithm 3. Chien Search Algorithm for locating and correcting errors Currently, the Berlekamp-Massey (BM) algorithm and the Euclidean algorithm are the main computational methods [16][17][18] for decoding long BCH codes. The Euclidean algorithm requires a larger computational load.…”

Section: Cbch Codementioning

confidence: 99%

Radiation Environment-Constrained FPGA Reinforcement Technology and Reliability Research Utilizing Error Control Coding

Zhang,

2024

IEEE Access

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In the radiation work environment of nuclear power plants and similar facilities, radiation can induce Single Event Upsets (SEUs) and even Multiple Bit Upsets (MBUs) in Field-Programmable Gate Arrays (FPGAs) and related devices. The hardware reinforcement techniques for FPGAs have strict material requirements and high costs, making implementation challenging. In contrast, FPGA software reinforcement techniques utilize error control coding to strengthen FPGA memory and combine with FPGA dynamic reconfiguration technology to reinforce the encoding and decoding modules. In this study, a BRAM fault injection experimental system is designed using Vivado to compare the reinforcement measures such as Hamming code, interleaved Hamming code, interleaved cyclic code, BCH code, and triple modular redundancy. Mathematical methods are employed to calculate their reliability performance indicators. The conclusion is that BCH (31,16,3) code exhibits the highest reliability, consumes the most resources, and can correct all errors of three bits or fewer. On the other hand, matrix interleaved code (28,16) can address the majority of MBUs, correcting all burst errors of four bits or fewer and some sporadic errors while utilizing relatively fewer resources.

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Section: Cbch Codementioning

confidence: 99%

Radiation Environment-Constrained FPGA Reinforcement Technology and Reliability Research Utilizing Error Control Coding

Zhang,

2024

IEEE Access

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“…Traditional RS coder/decoders are shift registersbased sequential circuits [6,7] . After certain shift latency, RS coders are clocked out in a consecutive order.…”

Section: Parallel Reed-solomon Eccmentioning

confidence: 99%

Fault-tolerant design of spaceborne mass memory system

Zhang

Chang

Gao

et al. 2010

Trans. Tianjin Univ.

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Abstract：A fault-tolerant spaceborne mass memory architecture is presented based on entirely commercial-off-theshelf components. The highly modularized and scalable memory kernel supports the hierarchical design and is well suited to redundancy structure. Error correcting code (ECC) and periodical scrubbing are used to deal with bit errors induced by single event upset. For 8-bit wide devices, the parallel Reed Solomon(10, 8) can perform coder/decoder calculations in one clock cycle, achieving a data rate of several Gb/s. In space environment, ECC combined with periodical scrubbing is appropriate and it reduces the word error rate by 5 orders of magnitude with 1% timing overhead and small hardware expenditure. Keywords：fault-tolerant memory architecture; data integrity; parallel Reed-Solomon codec In space environment, electronic devices are exposed to ionizing radiation such as electrons, protons and heavy ions. This results in a permanent loss after the accumulation of radiation and transient effects induced by single particles, such as single event upset (SEU) and single event latch-up (SEL) [1] . Both the single event effects (SEEs) are induced by electron-hole generated in silicon along the track of energetic particles. The total dose radiation effects can be reduced by using suitable shields. On the other hand, the susceptibility of SEE does not change significantly with shielding. As a consequence, only the presence of SEEs is considered in this paper.To deal with these issues, a typical approach is the development of space qualified electronic devices based on special and expensive technology processes. The use of such components implies some drawbacks such as high cost due to the special technology and small number of produced parts and low performances compared with commercial-off-the-shelf (COTS) components. Moreover, the requirements of short latency time, high throughput and storage capabilities cannot be satisfied by space qualified components and make the choice of COTS mandatory [2,3] . The fault-tolerant mass memory presented in this paper is based on COTS components.

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“…In the first stage of h(s) calculation, the 2,3,4 and 5 dimensional determinants are calculated. In the second stage, the are selected according to e and the coefficients of E r ( e ) (2) are computed. Table 1 shows the FPGA synthesis result of each stage of the pipelined core circuit with a commercial FPGA (Xilinx Virtex-I1 Pro).…”

Section: Core Architecturementioning

confidence: 99%

“…See, for example, [2] and references therein. These decoders, however, cannot achieve 40 Gbps data rate as a single decoder because of their direct implementation of conventional sequential algorithms with conditional branches, such as BerlekampMassey or (extended) Euclid algorithms.…”

Section: Introductionmentioning

confidence: 98%

An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability

Yamane

Katayama

2003

2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698)

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We present algorithm and IP design of a parallel ReedSolomon decoder with up to 8-byte random error correcting capability. The decoder soft-IP'consists of a core that can be designed as parallel combinational circuits of around 62K primitive gates and a peripheral that can he arranged flexibly depending on codeword configurations. The technology mapping results with even commercial FPGA demonstrates that a single core can achieve a throughput well over 40 Gbps when it is 4-stage pipelined. A single decoder design can process N-interleaved codewords efficiently if the core is operated in a time division mult,iplexing manner.

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A new scalable VLSI architecture for Reed-Solomon decoders

Cited by 52 publications

References 13 publications

Radiation Environment-Constrained FPGA Reinforcement Technology and Reliability Research Utilizing Error Control Coding

Radiation Environment-Constrained FPGA Reinforcement Technology and Reliability Research Utilizing Error Control Coding

Fault-tolerant design of spaceborne mass memory system

An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability

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