Fault-tolerant design of spaceborne mass memory system

Abstract

Abstract：A fault-tolerant spaceborne mass memory architecture is presented based on entirely commercial-off-theshelf components. The highly modularized and scalable memory kernel supports the hierarchical design and is well suited to redundancy structure. Error correcting code (ECC) and periodical scrubbing are used to deal with bit errors induced by single event upset. For 8-bit wide devices, the parallel Reed Solomon(10, 8) can perform coder/decoder calculations in one clock cycle, achieving a data rate of several Gb/s. In space environment, ECC combined with periodical scrubbing is appropriate and it reduces the word error rate by 5 orders of magnitude with 1% timing overhead and small hardware expenditure. Keywords：fault-tolerant memory architecture; data integrity; parallel Reed-Solomon codec In space environment, electronic devices are exposed to ionizing radiation such as electrons, protons and heavy ions. This results in a permanent loss after the accumulation of radiation and transient effects induced by single particles, such as single event upset (SEU) and single event latch-up (SEL) [1] . Both the single event effects (SEEs) are induced by electron-hole generated in silicon along the track of energetic particles. The total dose radiation effects can be reduced by using suitable shields. On the other hand, the susceptibility of SEE does not change significantly with shielding. As a consequence, only the presence of SEEs is considered in this paper.To deal with these issues, a typical approach is the development of space qualified electronic devices based on special and expensive technology processes. The use of such components implies some drawbacks such as high cost due to the special technology and small number of produced parts and low performances compared with commercial-off-the-shelf (COTS) components. Moreover, the requirements of short latency time, high throughput and storage capabilities cannot be satisfied by space qualified components and make the choice of COTS mandatory [2,3] . The fault-tolerant mass memory presented in this paper is based on COTS components.

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