An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability

Yamane, Toshiyuki; Katayama, Y.

doi:10.1109/icme.2003.1221344

Cited by 2 publications

(2 citation statements)

References 6 publications

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“…The syndrome computation block calculates all syndromes S i (0 ≤ i ≤ 15) by putting the roots of generator polynomial G(x) into the received codeword polynomial R(x) in Eq. (6). As shown in Fig.…”

Section: Four Parallel Syndrome Computation Blockmentioning

confidence: 82%

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High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems

Choi

Ahn

Lee

2011

IEICE Trans. Commun.

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This paper presents a high-throughput low-complexity four-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. Four-parallel processing is used to achieve 12-Gbps data throughput and low hardware complexity. Also, the proposed pipelined folded Degree-Computationless Modified Euclidean (fDCME) algorithm is used to implement the key equation solver (KES) block, which provides low hardware complexity for the RS decoder. The proposed four-parallel RS decoder is implemented 90-nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can be operated at a clock frequency of 400 MHz and has a data throughput 12.8-Gbps. The proposed four-parallel RS decoder architecture has high data processing rate and low hardware complexity. Therefore it can be applied in the FEC devices for next-generation high-rate WPAN systems with data rate of 10-Gbps and beyond.

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Section: Four Parallel Syndrome Computation Blockmentioning

confidence: 82%

“…To get a high throughput, parallel processing method can be a best solution for the hardware design. The one-shot Reed-Solomon encoder/decoder scheme [5], [6], which is based on parallel combinational circuit, can be a representative example for high throughput RS decoder.…”

Section: Introductionmentioning

confidence: 99%