A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/)

Abstract

A low latency architecture to compute the multiplicative inverse and division in a finite field GF(2 ) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers (2 ) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit.Index Terms-Finite field division, finite field inverse, finite field multiplier, VLSI architecture.

FPGA implementation of a BCH Codec for free space optical communication system

“…Expression (3) can be realized either in sequential or combinatorial manner. We have used a combinational design to speed up the inverse computation [8]. The inverse computing block is shown in Fig.2 (b).…”

A low-area, high-speed, processor array architecture for field ALU over GF (2^m)

“…Inversion architectures based on Euclid's algorithm require polynomial division and multiplication for each iteration, which demands a high computational power, which increases the implementation area as well as the critical path delay [2]. Inverters based on Fermat's theorem require recursive squaring and multiplication over GF(2 m ) [16], [17]. Inverters based on this technique require m-1 multiplications and m-2 squaring to calculate inversion [2].…”