2007 ITI 5th International Conference on Information and Communications Technology 2007
DOI: 10.1109/itict.2007.4475666
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A low-area, high-speed, processor array architecture for field ALU over GF (2<sup>m</sup>)

Abstract: We propose a novel, low-area, high-speed architecture for the basic operations over GF(2 m ). The proposed architecture is a processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. We use the National Institute of Standard and Technology recommended polynomials, which makes our design secure and more suitable for cryptographic applications. The proposed architec… Show more

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