A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

Abstract

Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to implement in residue number system (RNS). In the absence of an efficient solution to scale an integer directly in residue domain by a programmable power-of-two factor, improvised architecture by cascading fixed RNS scaling-by-two blocks has been previously presented. However, its area complexity and time complexity are worse than a hybrid solution leveraging on binary shifting through efficient residue-to-binary and binary-to-residue conversions. This paper presents a new algorithm for scaling in RNS by a programmable power-of-two factor. The proposed scaling algorithm breaks the inter-modulus dependency and produces a parallel architecture incurring no more than two logarithmic shifters, one-stage of carry-save adder and a modulo adder in any modulus channel. Comparing with the only available and most efficient hybrid programmable power-of-two scaler for the same moduli set, our proposed design has not only significantly reduced the critical path delay by 52.2%, 52.8%, 53.1%, and 53.2% for , 6, 7, and 8, respectively, but also cut down the area by 14.1% on average based on CMOS 0.18 standard cell based implementation. In addition, our proposed design has effectively reduced the total power consumption by 43.8% and the leakage power by 20.6% on average. Index Terms-Digital signal processing, power of two, residue number system, scaling.

A new area and power efficient DCT circuits using sporadic logarithmic shifters

“…The design can be used to implement exact or approximated DCTs. To minimize the complexity, new Sporadic Logarithmic Shifters (SLS) [24] are applied into the RMs to replace the conventional barrel shifters [25] and logarithmic shifters [26]. It has been shown in [24] that the complexity of SLSs drops further when its total amount of different shifts decreases.…”

New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

“…The work that has been published so far regarding scaling the RNS deals either with moduli sets of general form or with the traditional set. The main scalers that deal specifically with the traditional moduli set M 2 = {2 n + 1, 2 n , 2 n − 1} are presented in [7][8][9][10][11][12][13]. Those that are most efficient in terms of different metrics are presented in [12,13].…”

New algorithms and VLSI architectures for efficient RNS computations

“…The total processing time is k clock cycles, where k is the number of moduli. In subsequent years, many new techniques have been proposed and they can be categorized into scaling schemes with fixed scaling constant [Gri88], [Gri89], [She89a], [Bar95], [Ulm98], [Gar99], [Ye08], [Kon09], [Ma10], [Cha11] and with programmable powers-of-two scaling constant [Mey03], [Car05], [Low12].…”

“…The scaling schemes proposed in [Mey03], [Gri89] and [She89a] are designed for programmable powers-of-two scaling constant. They are formulated based on either division remainder zero [Mey03], [Car05] or the CRT [Low12]. For the schemes formulated based on division remainder zero, the moduli have to be chosen to be odd and pairwise relatively prime integers.…”

“…As suggested in [Car05], the sign detection and parity detection circuits can be implemented by using the methods suggested in [Mil85] and [Lu92], respectively with an additional redundant modulus. On the other hand, the scheme in [Low12] exploits the numeral properties of RNS and the CRT to formulate an efficient programmable powers-of-two scaling algorithm for the moduli set {2 n 1, 2 n , 2 n +1}. The computations in each modulus channel can be carried out in parallel by using at most two logarithmic shifters, onestage of carry save adder and a modulo adder.…”