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In a recent publication [l], we introduced the main outlines of a new algorithm for division in Residue Number System, which can be applied to any moduli set. Simulation results proved that the algorithm was many times faster than most competitive published work [2]. Determining the position of the most significant nonzero bit of any residue number in that algorithm is the major speed limiting factor. In this paper, we customize the same algorithm to serve two specific moduli sets: (2k,2k -1,2"l -1) and (2k + 1, 2k, 2k -l), and thus, eliminate that speed limiting factor. Based on this work, hardware needed to determine most significant bit position has been reduced to a single adder. Therefore, computation time and hardware requirements are substantially improved. This would enable RNS to be a stronger force in building general purpose computers.

The Viterbi algorithm is a fundamental signalprocessing technique used in different communication systems. An improved, implemented, and tested approximate squaring function for the Viterbi algorithm is introduced in this paper. The implementation of this improved squaring function is based on combinational logic design. The performance of this new approach has been verified by implementing a 7-bit squaring function chip in a 2-m CMOS technology. The active integrated circuit area of the chip was 380 2 400 m 2 , and the delays through this area were 5.7 and 3.0 ns for rising and falling edges, respectively.Compared with the design introduced in [3], this approach reduces error associated with approximation, simplifies the complexity of realization, reduces the integrated circuit area by at least 40%, and increases the speed by about 100%.Index Terms-Implementation, squaring function, very-largescale integration (VLSI) combinational logic design, Viterbi algorithm.

In earlier publications, many researchers have addressed the problem of residue-to-binary conversion for the popular moduli set [Formula: see text], where [Formula: see text] is a positive integer greater than 1. In this paper, we are proposing, potentially, the fastest converter ever for this moduli set with the least hardware requirements. Moreover, the paper revisits the extended three-moduli set [Formula: see text], where [Formula: see text] is a positive integer such that [Formula: see text]. This paper proposes an efficient residue-to-binary converter with an adjustable structure. The proposed structure allows increasing the dynamic range at a cost of two gates per bit. When compared with a similar published work for the extended moduli set, the proposed extended converter showed significant reductions in area by 9.9–13.4%, in delay by 16.9–24.1% and in power consumption by 10.6–16.7%.