Efficient digital sweep oscillator with extremely low sweep rates

Hiasat, A.A.; Alkhateeb, Abedalrhman

doi:10.1049/ip-cds:19982396

Cited by 13 publications

(30 citation statements)

References 7 publications

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“…This technique is known as fractional addressing and is utilized to reduce the level of spurious harmonic distortion. Another chirp signal generator in which fractional addressing is utilized, was reported in [8]. The major disadvantage is that it requires the implementation of two independent chirp generators in order to evaluate the phase difference between the two generated chirp signals.…”

Section: Generatorsmentioning

confidence: 99%

A Unique Parallel Processing Technique for Generating Digital Chirp Signals for the Applications of Synthetic Aperture Radar

Samarah

Albashar

Loffeld

2011

2011 UKSim 5th European Symposium on Computer Modeling and Simulation

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This paper proposes a unique parallel processing technique to generate a high bandwidth digital chirp signal up to 320 MHz with 200 MHz clock frequency using the approximation of the piecewise parabolic interpolation for the applications of radar, particularly Synthetic Aperture Radar (SAR). In this work, a smart parallel processing technique with 4 threads is completely derived, implemented and exploited to increase the bandwidth of the generated chirp signals using a hybrid system based on direct digital frequency synthesizer with low cost and minimal hardware overhead, in addition to having a smaller ROM size with respect to the other existing techniques in the literature.

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Section: Generatorsmentioning

confidence: 99%

A Unique Parallel Processing Technique for Generating Digital Chirp Signals for the Applications of Synthetic Aperture Radar

Samarah

Albashar

Loffeld

2011

2011 UKSim 5th European Symposium on Computer Modeling and Simulation

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“…The (2 p − 1) modular adder has an area and delay of 3p log 2 p + 5p and 2 log 2 p + 3 , respectively [19,20]. The area and delay of a 2 p binary adder are 3 2 log 2 p + 5p and 2 log 2 p + 3 , respectively [19,20]. The modified modulo 2 n adder has an area and delay of 3 2 p log 2 p + 12p and 2 log 2 p + 5 , respectively [19].…”

Section: Comparison and Vlsi Realizationmentioning

confidence: 99%

“…The area and delay of a 2 p binary adder are 3 2 log 2 p + 5p and 2 log 2 p + 3 , respectively [19,20]. The modified modulo 2 n adder has an area and delay of 3 2 p log 2 p + 12p and 2 log 2 p + 5 , respectively [19]. However, the area and delay of the (2 p + 1) modular adder are 4.5p log 2 p + 0.5p + 6 and 2 log 2 p + 3 , respectively [20].…”

Section: Comparison and Vlsi Realizationmentioning

confidence: 99%

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New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

Hiasat

2018

Computers

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This work proposes the first scaler designed specifically for the three-moduli set M 1 = { 2 n + 1 − 1 , 2 n , 2 n − 1 } . Hence, there is no other functionally similar scaler to compare the proposed scaler with. However, when compared with the latest published scalers for a different moduli set, M 2 = { 2 n + 1 , 2 n , 2 n − 1 } , the proposed scaler has a better area and power performance, while it requires a longer time delay. As demonstrated in earlier publications, replacing the ( 2 n + 1 ) channel in the M 2 moduli set by the ( 2 n + 1 − 1 ) channel, to form the M 1 moduli set, considerably improves the overall time performance of residue-based multiply–accumulate arithmetic units.

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“…This technique is known as fractional addressing and is utilized to reduce the level of spurious harmonic distortion. Another chirp signal generator in which fractional addressing is utilized, was reported in [5]. The major disadvantage is that it requires the implementation of two independent chirp generators in order to evaluate the phase difference between the two generated chirp signals.…”

Section: Introductionmentioning

confidence: 99%

Synthetic Aperture Radar System Using Digital Chirp Signal Generator Based on the Piecewise Higher Order Polynomial Interpolation Technique

Samarah

2014

2014 International Conference on Computational Intelligence and Communication Networks

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This paper shows the integration of a new digital chirp signal generator based on the piecewise higher order interpolation technique with a Synthetic Aperture Radar system (SAR). This new technique will support this kind of radar system in order to enhance the performance and the resolution of the output images and in the same time reduce the hardware complexity and the overall cost. This work presents an improved system using the optimization of the piecewise higher order interpolation, to generate digital chirp signals using a hybrid system based on direct digital frequency synthesizer with low cost and minimal hardware overhead, in addition to having a smaller ROM size with respect to the other existing techniques in the literature.

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Efficient digital sweep oscillator with extremely low sweep rates

Cited by 13 publications

References 7 publications

A Unique Parallel Processing Technique for Generating Digital Chirp Signals for the Applications of Synthetic Aperture Radar

A Unique Parallel Processing Technique for Generating Digital Chirp Signals for the Applications of Synthetic Aperture Radar

New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

Synthetic Aperture Radar System Using Digital Chirp Signal Generator Based on the Piecewise Higher Order Polynomial Interpolation Technique

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