New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

Hiasat, A.A.

doi:10.3390/computers7030046

Cited by 10 publications

(2 citation statements)

References 18 publications

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“…Paper [66] uses RNS to improve the digital filtering speed. Work [67] is devoted to the choice of RNS moduli set for efficient hardware implementation of computations. The proposed set weakens the requirements for energy consumption and device area, but increase PEs delay.…”

Section: Computations In the Residue Number Systemmentioning

confidence: 99%

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Nagornov,

Lyakhov,

Bergerman

et al. 2024

IEEE Access

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The technology development greatly increases the amount of digital visual information. Existing devices cannot efficiently process such huge amounts of data. The technical characteristics of digital image processing (DIP) devices and systems are being actively improved to resolve this contradiction in science and technology. The state-of-the-art methodology includes a huge number of very diverse approaches at the mathematical, software, and hardware implementation levels. We have analyzed all modern trends to improve the technical characteristics of DIP devices and systems. The main distinguishing feature of this review is that we are not limited to considering various aspects of neural network image processing, to which the vast majority of both review and research papers on the designated topic are devoted. Review papers on the subject under consideration are analyzed. Various mathematical and arithmetic-logical methods for improving the characteristics of image processing devices are described in detail. Original and significant architectural and structural solutions are analyzed. Promising neural network models of visual data processing are characterized. Hardware platforms for the design and operation of DIP systems that are efficient in terms of resource costs are considered. The most significant improvements achieved through the hardware implementation of models and methods on field-programmable gate arrays and application-specific integrated circuits are noted.INDEX TERMS High-performance computing, low-area design, low-power device, energy-efficient architecture, neural network, hardware accelerator, FPGA, ASIC.

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Section: Computations In the Residue Number Systemmentioning

confidence: 99%

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Nagornov,

Lyakhov,

Bergerman

et al. 2024

IEEE Access

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“…The chosen moduli set consists of an even modulus 2 n with remaining moduli of type 2 m − 1. Although a few contributions have been made regarding the design of RNS scalers for the aforementioned three-moduli sets [30,31], scaling problems with programmability features for this class of moduli sets have not yet been considered.…”

Section: Introductionmentioning

confidence: 99%

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 ⁿ ⁺ ^p , 2 ⁿ − 1, 2 ⁿ ⁺¹ − 1}

2020

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Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)–based DSPs, scaling represents a performance bottleneck based on the complexity of inter‐modulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well‐known moduli sets {2n − 1, 2n, 2n + 1} and {2n, 2n − 1, 2n+1 − 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic‐friendly moduli set {2n+p, 2n − 1, 2n+1 − 1}. The proposed algorithm yields high speed and energy‐efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed‐radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.

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General Frameworks for Designing Arithmetic Components for Residue Number Systems

Hiasat

2020

Advances in Intelligent Systems and Computing

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New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

Cited by 10 publications

References 18 publications

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 ⁿ ⁺ ^p , 2 ⁿ − 1, 2 ⁿ ⁺¹ − 1}

General Frameworks for Designing Arithmetic Components for Residue Number Systems

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New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

Cited by 10 publications

References 18 publications

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 n + p , 2 n − 1, 2 n +1 − 1}

General Frameworks for Designing Arithmetic Components for Residue Number Systems

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Product

Resources

About

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 ⁿ ⁺ ^p , 2 ⁿ − 1, 2 ⁿ ⁺¹ − 1}