A new area and power efficient DCT circuits using sporadic logarithmic shifters

Abstract

Discrete Cosine Transform (DCT) is by far the most widely adopted transformation in digital image and video processing. Particularly for applications in mobile and smart devices, the required DCT needs to be realized with small circuit area and low power cost. In this paper, a new area-and power-efficient DCT architecture design is proposed. To reduce the area and power cost, temporal redundancy in matrix-vector multiplication is eliminated by time-multiplexing reconfigurable multipliers. To further reduce the complexity, a new minimization algorithm is proposed to maximize the utilization of the newly developed sporadic programmable shifters. Our experimental results on FPGA show significant circuit area reduction by at least 39.0% and power-efficiency improvement by at least 12.3% over existing advanced DCT circuits reported in the literature.

Approximate adder design with simplified lower-part approximation

“…Addition is one of the heavily used arithmetic operations in many applications, and adders consume a significant amount of power and energy, which leads to hot-spot locations on processors [1]. Computationally intensive applications, such as image processing, machine learning, and data mining, may have inherent error tolerance, and a certain amount of computation error is acceptable in these applications [2,3,4,5,6]. Therefore, the design of efficient approximate adders that reduce power and energy has drawn great attention, and a large number of approximate adders have been proposed in the recent years [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29].…”

Hardware Efficient Integer Discrete Cosine Transform for Efficient Image/Video Compression

“…It achieves good compression performance with reduced computation cost by truncating a couple of least significant bits (LSB), most significant bits (MSB), and some zero columns. Another design was proposed recently in [31] by Chen et. al.…”

“…al. Compared with this paper, the main contribution in [31] is a new efficient DCT circuit implementation by using double base number system and an algorithm to minimize distinct shift counts. The design relies on existing Int-DCT coefficients for circuit implementation.…”