New algorithms and VLSI architectures for efficient RNS computations

Abstract

Residue Number System (RNS) is a non-weighted number system emerging as a promising substitute of two's complement number system for data representation in high-speed and lowpower digital signal processing. In RNS, arithmetic operations, such as addition, subtraction and multiplication, can be carried out at a faster speed due to the avoidance of carry propagation. Nonetheless, the arithmetic operations such as sign detection, scaling, base transformation and error decoding, are generally more difficult to be implemented in RNS. This thesis aims to tackle these difficult RNS operations by designing simple and efficient algorithms and architectures. In this thesis, a fast and area efficient 2 n signed integer RNS scaler for the moduli set {2 n −1, 2 n , 2 n +1} is proposed. The complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. As a result, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup and 32.5% of total power reduction compared to the state-of-art designs. In addition, a new concept of base transformation is introduced to reduce the overall arithmetic processing costs of multi-base RNS. The exploration into this new concept is motivated by the overkill of arithmetic operator sizes in RNS-based digital signal processors (DSPs) due to the List of Abbreviations CRT Chinese Remainder Theorem CSA Carry Save Adder