A V/SUB be/(T) model with application to bandgap reference design

Lin, Sheng-Feng; Salama, C.A.T.

doi:10.1109/jssc.1985.1052470

Cited by 27 publications

(3 citation statements)

References 7 publications

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“…In order to allow simulations of devices fabricated in different materials and to make the model simulator-independent, a temperature dependent bandgap voltage has been added to the model equations. The formulation suggested in [3] has been selected, ,…”

Section: Temperature Dependent Bandgap Voltagementioning

confidence: 99%

MMIC : composants - Transistors, technologies et modélisation

Dambrine¹,

Belot²,

Chevalier³

2015

Électronique

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Paul Malzac (Silvaco), and Adam Divergilio (Tektronix). Many thanks go also to Marek Mierzwinski (Tiburon) and Geoffrey Coram (Analog Devices) for discussions about and help with the Verilog-A implementation, to Prof. J.-C. Perraud (CAEN) for feedback regarding the prototype implementation in SPICE3F test simulations and, finally, to A. Chakravorty, K.-E. Moebus, and S. Komarow for their effort in implementing a working Verilog-A implementation and in performing thorough model testing.The HICUM group would like to thank especially ATMEL Germany (Heilbronn), STM (Grenoble, France), IBM (Burlington, USA) and Jazz Semiconductor (Newport Beach, USA) for financial support. We also appreciate the software donations from Agilent, Applied Wave Research, Cadence, Mentor Graphics and XMOD Technologies as well as wafer access from Atmel Germany, Infineon (Munich, Germany), Jazz Semiconductor, Skyworks (Newbury Park, USA), STM and TSMC (Hsinchu, Taiwan) for measurements and experimental model verification.HICUM

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Section: Temperature Dependent Bandgap Voltagementioning

confidence: 99%

MMIC : composants - Transistors, technologies et modélisation

Dambrine¹,

Belot²,

Chevalier³

2015

Électronique

View full text Add to dashboard Cite

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“…There are several articles describing the temperature characteristics of base-emitter junction [8][9][10]. Fig.…”

Section: Bandgap Core Equationsmentioning

confidence: 99%

An area and power optimization technique for CMOS bandgap voltage references

Tajalli

Chahardori

Khodaverdi

2009

Analog Integr Circ Sig Process

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This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in the technology and also the area of bipolar transistors. The proposed technique does not depend on a special process and can be applied for designing bandgap reference circuits with different topologies.

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“…An implementation in 5 µm CMOS was presented by Lin and Salama [43]. They implemented the scaling of ∆V BE,comp by means of a resistor ratio, so that non-integer values can be used.…”

Section: Using a Temperature-dependent Bias Current Ratiomentioning

confidence: 99%