This paper presents the first CMOS smart temperature sensor that is accurate to within ±0.1°C over the full military temperature range of -55°C to 125°C. This level of accuracy represents a 5-fold improvement in the state of the art [1,2]. This improvement is achieved by reducing circuit errors to the 0.01°C level through the extensive use of offset cancellation and dynamic element matching, combined with a room-temperature calibration.The operating principle of the sensor is illustrated in Fig. 13.1.1. Two substrate PNP transistors Q 1 and Q 2 are biased at a 5:1 current ratio. The difference in their base-emitter voltages ∆V BE is then proportional to absolute temperature (PTAT), and is digitized by a ∆Σ modulator. When the modulator's bitstream output bs=0, its input is 16⋅∆V BE , and when bs=1, its input is -V BE , the base-emitter voltage of a third transistor Q 3 . Since the modulator's feedback ensures that the average input is zero, the average value of the bitstream µ = 16⋅∆V BE / (V BE + 16⋅∆V BE ). This is the ratio of a PTAT voltage and a bandgap voltage, and is thus a digital representation of the chip's temperature [1]. The accuracy of this ratio is limited by V BE , which varies with the saturation current of Q 3 and the absolute value of the bias current I trim [3]. At a single temperature, I trim is adjusted to correct for the resulting temperature errors. This is done after packaging to incorporate the effects of mechanical stress.The front-end circuit that generates ∆V BE and V BE is shown in the right half of Fig. 13.1.2. A single pair of transistors Q L and Q R is used to generate both voltages. When bs=0, a multiplexer selects ∆V BE as the modulator's input voltage V ∆Σ . A set of 6 current sources, each with a nominal value of 1µA, is used to make a dynamically matched 5:1 bias current ratio [3]. The current source that generates the unit current is interchanged whenever bs=0, which ensures that any mismatches average out [4]. To average out mismatch between Q L and Q R , their bias currents are swapped within a ∆Σ cycle (using the control signal φ L ). The modulator then effectively processes the average of the two ∆V BE s.When bs=1, the multiplexer first selects V BEL (φ L =1) and then V BER (φ L =0). The average of the two is processed by the modulator. The bias current for the selected transistor is generated using the same six current sources mentioned above. One of them is switched on and off during consecutive ∆Σ cycles using the bitstream trim_bs of an 8b digital first-order ∆Σ modulator [5], while the other 5 are either on or off. This results in a bias current I trim that can be programmed between 0µA and 6µA with a resolution of 4nA, or 0.01°C. The quantization noise in trim_bs is averaged out by the analog ∆Σ modulator, while intermodulation between trim_bs and bs (a problem unsolved in [5]) is prevented by freezing the digital modulator when bs=0.The bias currents are generated by a chopped bias circuit (left half of Fig. 13.1.2) in such a way that V BE is not affected by the s...

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This paper presents a two-stage, compact, powerefficient 3 V CMOS operational amplifier with rail-to-rail input and output ranges. Because of its small die area of 0.04 mm', it is very suitable as a VLSI library cell. The floating class-AB control is shifted into the summing circuit, which results in a noise and offset of the amplifier which are comparable to that of a three stage amplifier. A floating current source biases the combined summing circuit and the class-AB control. This current source has the same structure as the class-AB control which provides a power-supply-independent quiescent current. Using the compact architecture, a 2.6 MHz amplifier with Miller compensation and a 6.4 MHz amplifier with cascoded-Miller compensation has been realized. The opamps have, respectively, a bandwidth-to-supplypower ratio of 4 MHdmW and 11 MHdmW for a capacitive load of 10 pF.

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