This paper presents the first CMOS smart temperature sensor that is accurate to within ±0.1°C over the full military temperature range of -55°C to 125°C. This level of accuracy represents a 5-fold improvement in the state of the art [1,2]. This improvement is achieved by reducing circuit errors to the 0.01°C level through the extensive use of offset cancellation and dynamic element matching, combined with a room-temperature calibration.The operating principle of the sensor is illustrated in Fig. 13.1.1. Two substrate PNP transistors Q 1 and Q 2 are biased at a 5:1 current ratio. The difference in their base-emitter voltages ∆V BE is then proportional to absolute temperature (PTAT), and is digitized by a ∆Σ modulator. When the modulator's bitstream output bs=0, its input is 16⋅∆V BE , and when bs=1, its input is -V BE , the base-emitter voltage of a third transistor Q 3 . Since the modulator's feedback ensures that the average input is zero, the average value of the bitstream µ = 16⋅∆V BE / (V BE + 16⋅∆V BE ). This is the ratio of a PTAT voltage and a bandgap voltage, and is thus a digital representation of the chip's temperature [1]. The accuracy of this ratio is limited by V BE , which varies with the saturation current of Q 3 and the absolute value of the bias current I trim [3]. At a single temperature, I trim is adjusted to correct for the resulting temperature errors. This is done after packaging to incorporate the effects of mechanical stress.The front-end circuit that generates ∆V BE and V BE is shown in the right half of Fig. 13.1.2. A single pair of transistors Q L and Q R is used to generate both voltages. When bs=0, a multiplexer selects ∆V BE as the modulator's input voltage V ∆Σ . A set of 6 current sources, each with a nominal value of 1µA, is used to make a dynamically matched 5:1 bias current ratio [3]. The current source that generates the unit current is interchanged whenever bs=0, which ensures that any mismatches average out [4]. To average out mismatch between Q L and Q R , their bias currents are swapped within a ∆Σ cycle (using the control signal φ L ). The modulator then effectively processes the average of the two ∆V BE s.When bs=1, the multiplexer first selects V BEL (φ L =1) and then V BER (φ L =0). The average of the two is processed by the modulator. The bias current for the selected transistor is generated using the same six current sources mentioned above. One of them is switched on and off during consecutive ∆Σ cycles using the bitstream trim_bs of an 8b digital first-order ∆Σ modulator [5], while the other 5 are either on or off. This results in a bias current I trim that can be programmed between 0µA and 6µA with a resolution of 4nA, or 0.01°C. The quantization noise in trim_bs is averaged out by the analog ∆Σ modulator, while intermodulation between trim_bs and bs (a problem unsolved in [5]) is prevented by freezing the digital modulator when bs=0.The bias currents are generated by a chopped bias circuit (left half of Fig. 13.1.2) in such a way that V BE is not affected by the s...

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This paper presents a power-and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm 2 ASIC, implemented in a low-voltage 0.18 m CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages, and employ a mismatch-scrambling technique to prevent the ripple signal associated with mismatch between these stages from limiting the dynamic range. In addition, an ultra-low-power LNA architecture is proposed to increase the power-efficiency of the receive circuitry. The ASIC has a compact, element-matched layout, and consumes less than 230 mW while receiving. Its functionality has been successfully demonstrated in 3-D imaging experiments.

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This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

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