A unified methodology for power supply noise reduction in modern microarchitecture design

Healy, Michael B.; Mohamood, Fayez; Lee, Hsien-Hsin S.; Lim, Sung Kyu

doi:10.1109/aspdac.2008.4484024

Cited by 7 publications

(14 citation statements)

References 14 publications

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“…Mohamood et al [4] proposed a design methodology for power integrity aware floorplanning using microarchitectural feedback to guide the module placement. Healy et al [5] presented an improved design methodology to combat the ever-aggravating high-frequency power supply noise (di/dt) in modern microprocessors. The ideas in [4], [5] are to build up dynamic controlling mechanisms at the microarchitecture level by dynamically monitoring the access patterns of microarchitecture modules and prevent the troublesome simultaneous switching activities among all the modules.…”

Section: Related Workmentioning

confidence: 99%

“…Healy et al [5] presented an improved design methodology to combat the ever-aggravating high-frequency power supply noise (di/dt) in modern microprocessors. The ideas in [4], [5] are to build up dynamic controlling mechanisms at the microarchitecture level by dynamically monitoring the access patterns of microarchitecture modules and prevent the troublesome simultaneous switching activities among all the modules. These works mainly focused on block-level design techniques, while in this paper, we investigate processor-level power gating protection strategies based on our detailed P/G noise analysis platform for MPSoC, and study the relationship between the performance degradation and the noise protection during powering on/off PUs.…”

Section: Related Workmentioning

confidence: 99%

“…Tight low power requirements force MPSoC to aggressively adopt low power techniques. While power gating can dramatically reduce leakage power in MPSoC, it exacerbates simultaneous switching noise on the power delivery network, and can result in performance degradation and even functional errors [4], [5], [6]. As that will be studied in Section 4, Fig.…”

Section: Introductionmentioning

confidence: 99%

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On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuitlevel MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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“…Tight low power requirements have forced MPSoC to aggressively adopt low power techniques such as dynamic voltage/frequency scaling, clock gating, and power gating [1,2]. While low power techniques like power gating can dramatically reduce power consumption for idle processing units (PUs), they exacerbate simultaneous switching noise (or di/dt noise) on the power delivery network.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed techniques include sleep transistor designs [3,4], decoupling capacitor insertion [5], and P/G noise-aware floorplanning [1,2,6]. Recently, power gating sequence scheduling [7][8][9] in a block or several blocks were proposed to tradeoff wake-up time for P/G noise reduction.…”

Section: Introductionmentioning

confidence: 99%

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Liu

Wang

et al. 2009

2009 IEEE Computer Society Annual Symposium on VLSI

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Power gating induced power/ground (P/G) noise is a major reliability problem facing by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large P/G noise and can cause timing divergence and even functional errors in surrounding processing units. P/G noise is different from thermal or energy which is an accumulative effect. The noise level should be predicted and victim circuits should be protected before the noise is induced. Hence, the power gating-aware scheduling problem with the consideration of P/G noise should be solved using an on-line method considering the run-time variation of tasks' execution time. In this paper, we formulate an on-line task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC. An efficient on-line Greedy Heuristic (GH) algorithm that adapts well to real-time variations is proposed to reduce noise protection penalty and improve MPSoC performance. Our experiments show that the algorithm can achieve on average 26% performance improvement together with on average 73% noise protection penalty saving compared with the conservative stop-go method. We also compare our technique with a twostep solution that computes a static schedule at compile time and make adjustment on the schedule according to runtime variations. For benchmark with larger task number, GH method achieves impressive performance improvement comparing with the two-step solution.

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Simulation and analysis of P/G noise in TSV based 3D MPSoC

Tao

Wang

et al. 2010

The 2010 International Conference on Green Circuits and Systems

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A unified methodology for power supply noise reduction in modern microarchitecture design

Cited by 7 publications

References 14 publications

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Simulation and analysis of P/G noise in TSV based 3D MPSoC

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