On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Xu, Yan; Liu, Weichen; Wang, Yu; Xu, Jiang; Chen, Xiaoming; Yang, Huazhong

doi:10.1109/isvlsi.2009.54

Cited by 9 publications

(6 citation statements)

References 25 publications

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“…In order to analyze the performance of SENoC, it is necessary to understand the impacts of power gating induced P/G noise among PUs in MPSoC. We build a P/G noise simulation and analysis platform and systematically explore MPSoC P/G noise behaviors under different power gating scenarios [33]. The noise behaviors serve as the basis for the P/G noise aware task management methodology based on SENoC.…”

Section: The Physical Model Of Power Gating-induced P/g Noisymentioning

confidence: 99%

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On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuitlevel MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.

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Section: The Physical Model Of Power Gating-induced P/g Noisymentioning

confidence: 99%

“…The simulations are based on the MPSoC P/G noise simulation and analysis platform, which is described in more detail in Section 4 and [33]. The P/G noise analysis platform is built up with HSPICE and C. Scheduling algorithms are implemented with C, Matlab, and SystemC, respectively.…”

Section: Implementation and Simulation Setupmentioning

confidence: 99%

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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“…There have been extensive researches on task scheduling and binding for MPSoC [13], [14], [15], [16], [17], [18], and also MPSoC power management [19], [20], [21], but few of them have addressed process variability.…”

Section: A Related Workmentioning

confidence: 99%

Variation-aware task scheduling and power mode selection for MPSoC power optimization

Momtazpour¹,

Goudarzi²,

Sanaei³

2010

2010 15th CSI International Symposium on Computer Architecture and Digital Systems

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Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm for MPSoCs. The proposed algorithm is able to maximize the total power yield of the chip under a given performance yield constraint by searching for the optimal task scheduling and power mode selection policy for a specified multiprocessor platform. Experimental results are gathered by simulating the algorithm with two different statistical analysis methods called Monte Carlo and Event-Reference-Table-based method. We have shown that by considering both leakage and frequency variation during the simultaneous selection of task scheduling and power mode switching policies, our algorithm achieves significant improvement over conventional methods.

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“…In order to analyze the performance of SENoC in the case study, it is necessary to understand the impacts of power gating induced P/G noise among PUs in MPSoC. We build a P/G noise simulation and analysis platform and systematically explore MPSoC P/G noise behaviors under different power gating scenarios [13]. The noise behaviors serve as the basis for the P/G noise aware task management methodology based on SENoC.…”

Section: The Physical Model Of Power Gating Induced P/g Noisementioning

confidence: 99%

A case study of on-chip sensor network in multiprocessor system-on-chip

Wang

Huang

et al. 2009

Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at run time could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively detect, report, and alleviate run-time threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used and explained in our case study to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.12% performance improvement compared with the traditional stop-go method with 1.4% area overhead in an 8*8-core MPSoC in 45nm.

show abstract

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Cited by 9 publications

References 25 publications

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Variation-aware task scheduling and power mode selection for MPSoC power optimization

A case study of on-chip sensor network in multiprocessor system-on-chip

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