No abstract

Many-tier systems are the future of 3D integration. In this work we explore power delivery system design for these large scale devices. We have developed a scalable many-tier design that contains one tier of processors and eight tiers of DRAM. These nine tiers comprise a 'set' that can be stacked any number of times. Previously, we have examined the dynamic and static power noise scaling behavior of various components of this system. Now, we present studies on two key aspects of power system architecture in these systems and their impact on power supply noise. First, we examine the addition of a dynamic noise-limiting turn-on policy and show that it can reduce dynamic power supply noise by 37% with almost no impact on system performance. Next, we present interesting results comparing different power/ground TSV topologies and show that a spread TSV distribution can lower both DC and dynamic power supply noise in the case that the many-tier stack contains low power tiers, such as memory tiers. We also show that ignoring TSV inductance when calculating dynamic noise can result in a 14.8% underestimate. IntroductionPerformance scaling in microprocessors has reached a major barrier because of the disparity between wire and transistor size scaling. 3D integration has emerged as a potential solution to this problem. However, there are many unresolved design issues related to 3D integration. In this work we explore power distribution network design for largescale 3D systems and present two techniques that reduce power supply noise for these large-scale systems.The largest factor creating transient noise is the so-called "first droop" noise that results from the interaction between inductance in the package and the on-and off-chip decoupling capacitance (decap) during sleep transitions. Modern microprocessors experience frequent power gating and sleep transition events as a result of aggressive power reduction techniques. These power gating events cause large transient changes in the current demand in the power supply network. For 3D systems the through silicon vias (TSVs) add inductance to that already in the package, exacerbating the power noise problem. In this work we use "dynamic noise" to refer to the first droop noise caused by power gating events and "IR-drop" to refer to the voltage drop in the power network during normal operation.Thermal impacts are another major factor that must be considered when designing 3D systems. Air-cooled heatsinks will be unable to cope with the power density of large-scale 3D systems. Recent work has focused on implementing micro-fluidic channels [1] onto the backs of 3D stacked ICs to remove heat using liquid-phase fluids. The heat removal capacity of these systems is very promising. In this work we

No abstract

We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.

Compression is seen as a simple technique to increase the effective cache capacity. Unfortunately, compression techniques either incur tag area overheads or restrict data placement to only include neighboring compressed cache blocks to mitigate tag area overheads. Ideally, we should be able to place arbitrary compressed cache blocks without any placement restrictions and tag area overheads. This paper proposes Touché, a framework that enables storing multiple arbitrary compressed cache blocks within a physical cacheline without any tag area overheads. The Touché framework consists of three components. The first component, called the "Signature" (SIGN) engine, creates shortened signatures from the tag addresses of compressed blocks. Due to this, the SIGN engine can store multiple signatures in each tag entry. On a cache access, the physical cacheline is accessed only if there is a signature match (which has a negligible probability of false positive). The second component, called the "Tag Appended Data" (TADA) mechanism, stores the full tag addresses with data. TADA enables Touché to detect false positive signature matches by ensuring that the actual tag address is available for comparison. The third component, called the "Superblock Marker" (SMARK) mechanism, uses a unique marker in the tag entry to indicate the occurrence of compressed cache blocks from neighboring physical addresses in the same cacheline. Touché is completely hardware-based and achieves an average speedup of 12% (ideal 13%) when compared to an uncompressed baseline.