Power delivery system architecture for many-tier 3D systems

Abstract

Many-tier systems are the future of 3D integration. In this work we explore power delivery system design for these large scale devices. We have developed a scalable many-tier design that contains one tier of processors and eight tiers of DRAM. These nine tiers comprise a 'set' that can be stacked any number of times. Previously, we have examined the dynamic and static power noise scaling behavior of various components of this system. Now, we present studies on two key aspects of power system architecture in these systems and their impact on power supply noise. First, we examine the addition of a dynamic noise-limiting turn-on policy and show that it can reduce dynamic power supply noise by 37% with almost no impact on system performance. Next, we present interesting results comparing different power/ground TSV topologies and show that a spread TSV distribution can lower both DC and dynamic power supply noise in the case that the many-tier stack contains low power tiers, such as memory tiers. We also show that ignoring TSV inductance when calculating dynamic noise can result in a 14.8% underestimate. IntroductionPerformance scaling in microprocessors has reached a major barrier because of the disparity between wire and transistor size scaling. 3D integration has emerged as a potential solution to this problem. However, there are many unresolved design issues related to 3D integration. In this work we explore power distribution network design for largescale 3D systems and present two techniques that reduce power supply noise for these large-scale systems.The largest factor creating transient noise is the so-called "first droop" noise that results from the interaction between inductance in the package and the on-and off-chip decoupling capacitance (decap) during sleep transitions. Modern microprocessors experience frequent power gating and sleep transition events as a result of aggressive power reduction techniques. These power gating events cause large transient changes in the current demand in the power supply network. For 3D systems the through silicon vias (TSVs) add inductance to that already in the package, exacerbating the power noise problem. In this work we use "dynamic noise" to refer to the first droop noise caused by power gating events and "IR-drop" to refer to the voltage drop in the power network during normal operation.Thermal impacts are another major factor that must be considered when designing 3D systems. Air-cooled heatsinks will be unable to cope with the power density of large-scale 3D systems. Recent work has focused on implementing micro-fluidic channels [1] onto the backs of 3D stacked ICs to remove heat using liquid-phase fluids. The heat removal capacity of these systems is very promising. In this work we

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

“…Prior work [13], [14] suggests that a distributed topology for PG TSVs is superior to both single, large TSVs and groups of clustered TSVs. These and other studies (Table I) also favor irregular TSV placement, in particular such that regions drawing significant current exhibit a higher TSV density.…”

“…This drop is the dominant cause of power-noise issues in 3D ICs. However, for large stacks, the TSV inductance which impacts transient noise should also be considered [13].…”

“…Our optimization methodology MoDo is presented in Section III; an experimental investigation is provided in Section IV. Our conclusions on optimizing deadspace for 3D ICs and its benefits are given in Section V. [25]) [19], [20] rarely aligned nonuniform; Thermal ≈ 2 − 40µm may be encouraged low -medium irregular small -medium contigous regions; [7] [8], [9], [27] possibly aligned nonuniform; Power/Ground ≈ 10 − 40µm strongly preferred low irregular small contigous regions; [7], [13], [14], [16] [11], [13], [14], [16] necessarily aligned nonuniform; Clock ≈ 2 − 20µm may be encouraged low irregular small contigous regions; [33] [33], [34] possibly aligned…”

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

“…TSVs are much smaller than off-chip wires, thereby enabling very wide bandwidth and high-speed communication between stacked dies. However, there exist several problems such as heat, TSV defects, and power delivery in 3D ICs [2], [3]. These problems need to be resolved to build reliable 3D ICs.…”

TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs

“…However 3D-ICs impose significant constraints on how and where the micro-channels could be located due to the presence of TSVs, which allow different layers to communicate. A 3D-IC usually contains thousands of TSVs which are incorporated with clustered or distributed topologies [8] [9]. These TSVs form obstacles to the micro-channels since the micro-channels cannot be placed at the locations of TSVs.…”