Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

Kim, Dae Hyun; Athikulwongse, Krit; Healy, Michael B.; Hossain, Mohammad Motaher; Jung, Moongon; Khorosh, Ilya; Kumar, Gokul; Lee, Young-Joon; Lewis, Dean L.; Lin, Tzu-Wei; Liu, Chang; Panth, Shreepad; Pathak, Mohit; Ren, Minzhen; Shen, Guanhao; Song, Taigon; Woo, Dong Hyuk; Zhao, Xin; Kim, Joungho; Choi, Ho Yong; Loh, Gabriel H.; Lee, Hsien-Hsin S.; Lim, Sung Kyu

doi:10.1109/tc.2013.192

Cited by 55 publications

(25 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…According to the 3D-Stacking approach multiple layers of DRAM memory are stacked together with a logic layer that can be application-specific ( [7,8]) or general purpose [9]. In Reference [7] the XNOR-POP architecture was designed to accelerate CNNs for mobile devices.…”

Section: D-stackingmentioning

confidence: 99%

“…In Reference [8] it is proposed an architecture for data intensive applications, where a PIM layer made of memory and application-specific logic is sandwiched between DRAM dies connected together using TSVs. An example of general purpose 3D-stacking is 3D-MAPS in Reference [9]. A multi-core structure is used, and every core is composed of a memory layer and a computing layer.…”

Section: D-stackingmentioning

confidence: 99%

See 1 more Smart Citation

Data Processing and Information Classification—An In-Memory Approach

Andrighetti

Turvani

Santoro

et al. 2020

Sensors

View full text Add to dashboard Cite

To live in the information society means to be surrounded by billions of electronic devices full of sensors that constantly acquire data. This enormous amount of data must be processed and classified. A solution commonly adopted is to send these data to server farms to be remotely elaborated. The drawback is a huge battery drain due to high amount of information that must be exchanged. To compensate this problem data must be processed locally, near the sensor itself. But this solution requires huge computational capabilities. While microprocessors, even mobile ones, nowadays have enough computational power, their performance are severely limited by the Memory Wall problem. Memories are too slow, so microprocessors cannot fetch enough data from them, greatly limiting their performance. A solution is the Processing-In-Memory (PIM) approach. New memories are designed that can elaborate data inside them eliminating the Memory Wall problem. In this work we present an example of such a system, using as a case of study the Bitmap Indexing algorithm. Such algorithm is used to classify data coming from many sources in parallel. We propose a hardware accelerator designed around the Processing-In-Memory approach, that is capable of implementing this algorithm and that can also be reconfigured to do other tasks or to work as standard memory. The architecture has been synthesized using CMOS technology. The results that we have obtained highlights that, not only it is possible to process and classify huge amount of data locally, but also that it is possible to obtain this result with a very low power consumption.in slow accesses compared to processors computing speed. This discrepancy in performance harms the computing abilities of the CPU, since the memory cannot provide data as quickly as required by the CPU. This problem is called Von Neumann bottleneck or Memory Wall. The idea that took form to solve this problem is to null the distance between processor and memory, removing the cost of data transfer and create a unit which is capable of storing information and of performing operation on them. This idea takes the name of Processing-in-Memory.Many in literature have approached the "in-memory" idea. Some narrowing the physical distance between memory and computation unit by creating and stacking different layers together. But even if the two units are moved very close to each other, they are still distinct components. Others exploited intrinsic functionality of the memory array or slightly modified peripheral circuitry to perform computation.Among the many example provided by literature, one of the best fitting representative of the PIM concept is presented in Reference [1]. In this work the proposed architecture is a memory array in which the cell itself is capable of performing logical operations aimed at solving Convolutional Neural Networks (CNN). In this paper, our main goal is to introduce a proper example of Processing-in-Memory, choosing Bitmap Indexing as an application around which the architecture is shaped. In th...

show abstract

Section: D-stackingmentioning

confidence: 99%

Section: D-stackingmentioning

confidence: 99%

Data Processing and Information Classification—An In-Memory Approach

Andrighetti

Turvani

Santoro

et al. 2020

Sensors

View full text Add to dashboard Cite

show abstract

“…Since multilayered electrical integrated circuits [12][13][14] are the prevailing industrial technology, future intrachip optical interconnects should be adapted to the multilayered structure, and an optical interlayer routing scheme will be needed. The proposed device, acting as a bidirectional switchable router between the layers of optical integrated circuits, would be an important component for realizing fully scalable, three-dimensional (3D) electro-optical integrated circuits.…”

Section: Introductionmentioning

confidence: 99%

Low-loss Electrically Controllable Vertical Directional Couplers

Tran

Kim

2017

Current Optics and Photonics

View full text Add to dashboard Cite

We propose a nearly lossless, compact, electrically modulated vertical directional coupler, which is based on the controllable evanescent coupling in a previously proposed graphene-assisted total internal reflection (GA-FTIR) scheme. In the proposed device, two single-mode waveguides are separate by graphene-SiO2-graphene layers. By changing the chemical potential of the graphene layers with a gate voltage, the coupling strength between the waveguides, and hence the coupling length of the directional coupler, is controlled. Therefore, for a properly chosen, fixed device length, when an input wave is launched into one of the waveguides, the ratio of their output powers can be controlled electrically. The operation of the proposed device is analyzed, with the dispersion relations calculated using a model of a one-dimensional slab waveguide. The supermodes in the coupled waveguide are calculated using the finite-element method to estimate the coupling length, realistic devices are designed, and their performance was confirmed using the finite-difference time-domain method. The designed 3 μm by 1 μm device achieves an insertion loss of less than 0.11 dB, and a 24-dB extinction ratio between bar and cross states. The proposed low-loss device could enable integrated modulation of a strong optical signal, without thermal buildup.

show abstract

“…Few 3D integrated memory-logic microprocessors are designed in academia. From the academia, first 3D memory-logic integrated system is fabricated using 130nm GF process, called 3D massively parallel processor with stacked memory (3D MAPS) [5,75] by Georgia Institute of Technology consists of 47,490 I/O TSVs and 6,540 dummy or thermal TSVs, used for heat-dissipation, shown in Figure 2.3. The die occupies an area of 25mm 2 .…”

Section: Overviewmentioning

confidence: 99%

“…With the increase in the number of integrated multi-core and memory blocks for a cloud server, the number of signal I/Os grows dramatically, hence there is an emerging need to develop high data-rate and low power I/O circuits [157,158]. Though 3D integration by stacking several layers of dies vertically using through-silicon via (TSV) I/O [133,29,31,159,37,75,160,5,96] provides a scalable integration, accumulated heat in top layers and complexity of heat removal techniques can limit the flexibility of the design [161,27,28]. As discussed in previous chapters, 2.5D integration by through-silicon interposers (TSIs) in common substrate has a strong heat dissipation capability [10,39].…”

Section: Introductionmentioning

confidence: 99%

2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

Dinakarrao¹

View full text Add to dashboard Cite

First and foremost, I would like to express the deepest gratitude to my advisor Prof. Yu Hao, for his invaluable support both in my research and life during all years of my work in NTU. I have been extremely fortunate to work under his supervision and I deeply appreciate his time, patience and support throughout my Ph.D. career. His assistance, constructive comments, and technical insights have always been most helpful in addressing my research issues. He taught me to set high standards for myself and made me realize the importance of global competence. For me, he sets a good example of what a researcher should be like: have enthusiasm towards research, always think out of box, and work hard to solve problems. I would like to express my special thanks to Dr. Yu Mingbin, Dr. Roshan Weerasekera, Prof. Siek Liter, Prof. Tan Chuan Seng, and Prof. Chang Chip-hong, for giving me generous amount of time whenever I needed some help. I also want to thank the Virtus and EEE GPO staff Gek Eng, Dorothy, David Robert, Karen, Chow Kam Wah, Christina, and many others who have been really friendly and patient to help me many times on administrative matters. I would like to express my thanks to my wonderful colleagues,

show abstract

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

Cited by 55 publications

References 12 publications

Data Processing and Information Classification—An In-Memory Approach

Data Processing and Information Classification—An In-Memory Approach

Low-loss Electrically Controllable Vertical Directional Couplers

2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

Contact Info

Product

Resources

About