A Sub-2 W 39.8–44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS

Raghavan, Bharath; Cui, Delong; Singh, Ullas; Maarefi, Hassan; Pi, Deyi; Vasani, Anand; Huang, Zhi; Catli, Burak; Momtaz, Afshin; Cao, Jun

doi:10.1109/jssc.2013.2279054

Cited by 31 publications

(13 citation statements)

References 11 publications

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“…Under such modest conditions, neglecting additional system-related overheads, the throughput coming in-and-out of the central unit is 381.4 Gb/s. As stated in [34], a Fig. 4.…”

Section: Backplane Interconnect Topologies and Impact Of Distributed mentioning

confidence: 88%

Real-Time Implementation Aspects of Large Intelligent Surfaces

Tataria

Tufvesson

Edfors

2020

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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With the potential to provide a clean break from massive multipleinput multiple-output, large intelligent surfaces (LISs) have recently received a thrust of research interest. Various proposals have been made in the literature to define the exact functionality of LISs, ranging from fully active to largely passive solutions. Nevertheless, almost all studies in the literature investigate the fundamental spectral efficiency performance of these architectures. In stark contrast, this paper investigates the implementation aspects of LISs. Using the fully active LIS as the basis of our exposition, we first present a rigorous discussion on the relative merits and disadvantages of possible implementation architectures from a radio-frequency circuits and real-time processing viewpoints. We then show that a distributed architecture based on a common module interfacing a smaller number of antennas can be scalable. To avoid severe losses with analog signal distribution, multiple common modules can be interconnected via a digital nearest-neighbor network. Furthermore, we show that with such a design, the maximum backplane throughput scales with the number of served user terminals, instead of the number of antennas across the surface. The discussions in the paper can serve as a guideline toward the real-time design and development of LISs.

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“…Under such modest conditions, neglecting additional system-related overheads, the throughput coming in-and-out of the central unit is 381.4 Gb/s. As stated in [34], a Fig. 4.…”

Section: Backplane Interconnect Topologies and Impact Of Distributed mentioning

confidence: 88%

Real-Time Implementation Aspects of Large Intelligent Surfaces

Tataria

Tufvesson

Edfors

2020

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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“…Signal integrity degradation induced by GDV in circuit designs was investigated in [18]- [20]. Preemphasis is applied to the modulated signal to compensate high-frequency loss in conventional NRZ and PAM signaling [9], [21]- [24]. DPWM signaling also improves signal integrity using a feedforward equalizer.…”

Section: Dpwm Preemphasismentioning

confidence: 99%

Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication

Wang

Buckwalter

2016

IEEE Trans. VLSI Syst.

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Double-edged pulsewidth modulation (DPWM)is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. This paper presents an 8-/9-bit line-coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buffering required in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for high-speed data recovery. The DPWM transceiver is implemented in a 45-nm CMOS Silicon on insulator and operates at 10 Gbit/s with 10 −12 bit error rate and consumes 96 mW. The power consumption of the 8-/9-bit coding hardware is 1.5 mW at 10 Gbit/s demonstrating low-power overhead.

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“…2(b). These analog delay lines are usually based on cascaded CML buffers [17], [18], or LC-cells [2], [19]- [21], which have been proved in ultra-high-speed applications such as 64 Gb/s [2]. Nonetheless, they cannot support a wide operation range because of their limited adjusting range.…”

Section: Introductionmentioning

confidence: 99%

A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

Lv¹,

Zheng²,

Zhao³

et al. 2018

JSTS

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A 2-40 Gb/s PAM4/NRZ dual-mode wireline transmitter with 4:1 MUX in 65-nm CMOS http://researchonline.ljmu.ac.uk/8698/ Article LJMU has developed LJMU Research Online for users to access the research output of the University more effectively.Abstract-This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-tozero (NRZ) modulation with a multiplexer (MUX)based two-tap feed-forward equalizer (FFE). An edgeacceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. Index Terms-Four-level pulse amplitude modulation (PAM4), non-return-to-zero (NRZ), edge-acceleration technique, linearity optimization, dual-mode wireline transmitter

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A Sub-2 W 39.8–44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS

Cited by 31 publications

References 11 publications

Real-Time Implementation Aspects of Large Intelligent Surfaces

Real-Time Implementation Aspects of Large Intelligent Surfaces

Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication

A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

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