A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

Abstract

A 2-40 Gb/s PAM4/NRZ dual-mode wireline transmitter with 4:1 MUX in 65-nm CMOS http://researchonline.ljmu.ac.uk/8698/ Article LJMU has developed LJMU Research Online for users to access the research output of the University more effectively.Abstract-This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-tozero (NRZ) modulation with a multiplexer (MUX)based two-tap feed-forward equalizer (FFE). An edgeacceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. Index Terms-Four-level pulse amplitude modulation (PAM4), non-return-to-zero (NRZ), edge-acceleration technique, linearity optimization, dual-mode wireline transmitter

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

“…The traditional 1/2 speed architecture MUX provides only a timing margin of 1 UI, when the data rate is 112 Gb/s, 1 UI is about 8.9 ps. To ensure the accuracy of the overall circuit timing, the 4:1 MUX based on 1/4 speed architecture is designed, which can extend the timing from 1 UI to 3 UI [5,[22][23][24].…”