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Abstract-This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feedforward equalizer (FFE) and a far-end crosstalk canceller (XTC) is implemented in the TX chip. The RX chip employs an adaptive quarter-rate 2-tap decision-feedback equalizer (DFE) and a baud-rate clock and data recovery (CDR). The power-efficient DFE uses the combination of the soft-decision technique and a new dynamic structure. The DFE adaption logic and baud-rate CDR logic share a set of error samplers to save power and area. A hybrid alternate clock scheme is proposed to satisfy the timing requirement and reduce the power consumption further. The measurement results show that the TX and RX chipset totally compensates for a Nyquist channel loss of more than 40 dB, and consumes only 70 mW from a 1.2 V supply when operating at 25 Gb/s.

We demonstrate continuous detectability of lO-Gb/s data from 0 to 675 km of standard single mode fiber without in-line dispersion compensation using a combination of a chirp, managed laser and tunable optical and electronic dispersion compensation at the receiver.