A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

Abstract

A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feedforward equalizer (FFE) and a far-end crosstalk canceller (XTC) is implemented in the TX chip. The RX chip employs an adaptive quarter-rate 2-tap decision-feedback equalizer (DFE) and a baud-rate clock and data recovery (CDR). The power-efficient DFE uses the combination of the soft-decision technique and a new dynamic structure. The DFE adaption logic and baud-rate CDR logic share a set of error samplers to save power and area. A hybrid alternate clock scheme is proposed to satisfy the timing requirement and reduce the power consumption further. The measurement results show that the TX and RX chipset totally compensates for a Nyquist channel loss of more than 40 dB, and consumes only 70 mW from a 1.2 V supply when operating at 25 Gb/s.

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

“…The DFE adaption logic [10] based on the sign-sign leastmean-square (SS-LMS) algorithm is designed in this work. As presented in Fig.…”

“…17 (a) is the expected eye height, when the data is higher than the expected eye height, the error data X is 1, otherwise is 0. The SS-LMS logic in [10] converts the DFE error (X) signal to the ISI error signal (S). The relationship between X and S is = − * * − .…”

“…The paper is organized as follows: Section II describes the architecture of the TX, section III details the receiver (RX), section IV introduces wideband clocking techniques, section V presents the measurement results, and this paper is concluded in Section Ⅵ. MUX (to convert half-rate data stream to full-rate data stream) based on the dynamic transmission-gate [10] is employed to trade off the power and speed. The TX includes a currentmode logic (CML) driver with a 3-tap FFE to realize the TX de-emphasis for pre-distorting the signal before transmission.…”

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

“…Source-series-terminated (SST) transmitters, a type of VML transmitter, have been applied in many low-power high-speed transmitters [7,8,9]. However, an inherent drawback of traditional SST transmitters is that their equalization capability is proportional to the power consumption [10,11]. Therefore, when the equalization capability increases, the power consumption of the output stage also increases.…”

Duty-cycle and phase spacing error correction circuit for high-speed serial link

“…As a solution for this, high-speed serial link transceiver usually employs multi-phase clocking which allows the use of a lower frequency clock for a given data rate [3,4]. The random mismatch, however, causes duty cycle error and unequal phase spacing of multi-phase clock which appear as deterministic jitter (DJ) degrading the performance of high-speed serial link [5,6,7,8].…”