This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.
This study presents an 8 Gbps low-power source-series terminated (SST) transmitter for high-speed serial links. The proposed transmitter consists of a novel hybrid 20:2 multiplexer followed by a three-tap feed-forward equalizer (FFE) and a shunt path SST driver. In addition, a high-precision impedance calibration circuit with slice unit replication is proposed to match the characteristic impedance of channel, whose maximum calibration error is 0.002%. Fabricated in 55-nm CMOS technology and has area of 0.024 mm 2 . Measurement results show that the transmitter achieves data rate of 8 Gbps while maintaining good performance. The transmitter has output swing of 510 mV with −6 dB post-tap equalization, and it consumes 15.1 mW under 1.2 V power supply.
This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.
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