A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Abstract

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

“…Therefore, it is strongly advised to implement a duty cycle corrector that consumes a small area. To maximize area efficiency, the method of performing a duty cycle correction with a PLL has been proposed [14]. However, there is a problem in that the pole-zero cancellation is not accurate due to the device mismatch and, in addition, uncanceled pole and zero increase the settling time of the comparator.…”

“…However, there is a problem in that the pole-zero cancellation is not accurate due to the device mismatch and, in addition, uncanceled pole and zero increase the settling time of the comparator. Moreover, their detection accuracies are severely affected (and degraded) by any offset voltages in duty cycle detection circuits [14,15], which is not a desirable factor in advanced CMOS technologies with higher device mismatches and offsets. A time-to-digital-conversion (TDC) based duty cycle detector is utilized in [16,17] to resolve the accuracy and variation issues by utilizing fine-resolution TDC circuits.…”