A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

Bai, Xu; Zhao, Jianzhong; Zuo, Shi; Zhou, Yumei

doi:10.1587/elex.16.20190356

Cited by 2 publications

(2 citation statements)

References 29 publications

(29 reference statements)

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“…The single-ended output impedance of the driver is 50 Ω. The larger series resistors are added, the wider the switch transistor is needed to ensure that the total resistance remains 50 Ω [21], [22]. wider the switch will bring parasitic load capacitance at the output node which will reduce the bandwidth.…”

Section: Introductionmentioning

confidence: 99%

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Ding

Jin

Zhou

2022

IEICE Trans. Fundamentals

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This brief presents A 16/32 Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067 mm 2 , while the proposed linearity enhanced part is 0.05×0.02 mm 2 and the total power consumption is 64.6 mW with a 1.1 V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.

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Section: Introductionmentioning

confidence: 99%

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Ding

Jin

Zhou

2022

IEICE Trans. Fundamentals

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“…From an application perspective, the driver needs to conform to different protocols. Moreover, because the integrity of high-speed signals is often affected by the channel loss of the transmission line, a feed-forward equalizer (FFE) is usually used in the driver, to compensate for channel loss [11][12][13]. In general, a baud-spaced FFE is usually used.…”

Section: Introductionmentioning

confidence: 99%

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

et al. 2022

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An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68.

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A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

Cited by 2 publications

References 29 publications

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

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