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Abstract-Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.Index Terms-Digital integrated circuits, domino logic style, dynamic circuits, negative differential resistance, noise-tolerant design.

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Load imbalance that deteriorates the system performance is a severe problem existing in 3GPP LTE networks. To deal with this problem, we propose in this paper a load balancing framework, which aims at balancing the load in the entire network, while keeping the network throughput as high as possible. In this framework, the objective is formulated as a network-wide utility function balancing network throughput and load distribution, and then it is transformed to an integer optimization problem under resource allocation constraints. After that, the complexity of the problem is analyzed, network structure constraints are presented, and a practical suboptimal algorithm, called Heaviest-First Load Balancing (HFLB), is proposed. Extensive simulation is made and the results show that using the HFLB algorithm the network can get significantly better load balancing while maintaining the same network throughput at the price of a bit more handovers compared with the traditional signal strength-based handover algorithm.