A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal-oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.

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VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro placement. Five major algorithms for placement are discussed: simulated annealing, force-directed placement, rein-cut placement, placement by numerical optimization, and evolution-based placement. The first two classes of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena. In each category, the basic algorithm is explained with appropriate examples. Also discussed are the different implementations done by researchers.

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Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current-voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

A well-known empirical rule for the demand of wireless communication systems is that of Edholm's law of bandwidth. It states that the demand for bandwidth in wireless short-range communications doubles every 18 months. With the growing demand for bandwidth and the decreasing cell size of wireless systems, terahertz (THz) communication systems are expected to become increasingly important in modern day applications. With this expectation comes the need for protecting users' privacy and security in the best way possible. With that in mind, we show that quantum key distribution can operate in the THz regime and we derive the relevant secret key rates against realistic collective attacks. In the extended THz range (from 0.1 to 50 THz), we find that below 1 THz, the main detrimental factor is thermal noise, while at higher frequencies it is atmospheric absorption. Our results show that high-rate THz quantum cryptography is possible over distances varying from a few meters using direct reconciliation, to about 220m via reverse reconciliation. We also give a specific example of the physical hardware and architecture that could be used to realize our THz quantum key distribution scheme. * Electronic address: carlo.ottaviani@york.ac.uk † Electronic address: stefano.pirandola@york.ac.uk exhibit very little degradation in performance compared to free-space optical links [9][10][11][12]. Under fog conditions, free-space optical links are completely blocked while THz links exhibit minimal impact. Similar transmission windows can be exploited at the MIR and FIR ranges, in particular, between 15 and 34 THz [13]. A detailed analysis of the propagation properties of THz signals for wireless communications in atmosphere can be found, for instance, in Ref. [14][15][16].An important aspect of THz communication is that of achieving the highest levels of security possible where secure distances need to range from 1 m up to 1 km. Applications for secure links include stealthy short distance communications between military personnel and vehicles (manned or unmanned). Security has been considered before in terms of THz communication by exploiting various characteristics and properties of the THz band [2,3]. Unfortunately, the security of all such 'classical' communication schemes have their limit in the sense that they can never be unconditionally secure. This problem can be fixed by quantum key distribution (QKD) [17][18][19]. QKD profits from the peculiar properties of quantum physics and quantum information [20][21][22], in particular the no-cloning theorem [23] and the monogamy of entanglement [24], to achieve levels of security that are not possible using classical cryptography.Continuous-variable (CV) QKD [19,25,26] has attracted increasing attention in the last years. This is due to the high rates achievable that allow one to approach the ultimate limit of point-to-point private communication [27][28][29], i.e., the Pirandola-Laurenza-Ottaviani-Banchi (PLOB) bound [27], equal to − log 2 (1 − T ) se-

Abstract-Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.Index Terms-Digital integrated circuits, domino logic style, dynamic circuits, negative differential resistance, noise-tolerant design.

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