On circuit techniques to improve noise immunity of CMOS dynamic logic

Abstract

Abstract-Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.Index Terms-Digital integrated circuits, domino logic style, dynamic circuits, negative differential resistance, noise-tolerant design.

A novel technique to improve noise immunity of CMOS dynamic logic circuits

“…It is also observed that the difference in dynamic noise immunity among the keepers are reduced when the input noise duration is extremely small. This is essential for the high performance operation of dynamic logic gates employing the proposed keepers [6].…”

“…However, this goal is not able to be materialized using a single field-effect transistor. It can be shown that I sp I nm has a lower bound of 1 V D V DD for MOS keepers with a monotonic and concave I-V characteristic [6]. In reality, the delay keeper strength I sp is often comparable to, if not greater than, the noise keeper strength I nm , as shown in Fig.…”

A Novel Enhanced Noise-Immunity Design Technique for Dynamic Logic Gates

“…While these noises always existed, in the past they had little impact on the performance of integrated circuits and were often neglected. It is the unstopped aggressive technology scaling in an effort to continuously improve chip performance and integration level that makes noise play an increasingly important role in comparison with conventional design metrics like area, speed and power consumption [2].…”

“…In comparison, the switching threshold voltage of static CMOS logic gate is typically around half the supply voltage [2] [3]. Therefore, dynamic logic gates inherently have less noise immunity than static CMOS logic gates and are the weak link in a high-performance VLSI chip designed using deep submicron process technology.…”

“…However, existing remedial techniques improve dynamic circuit noise tolerance at a significant cost in terms of one or more other important design metrics like circuit area, speed and power consumption [2] [8].…”