Abstract:Double-edged pulsewidth modulation (DPWM)is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. This paper presents an 8-/9-bit line-coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buffering required in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means … Show more
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