A spatial computing architecture for implementing computational circuits

Abstract

Abstract-To accelerate many computational software algorithms, designers are implementing them as computational circuits. These algorithms are diverse and include molecular dynamics, weather simulation, video encoding, and financial modelling. Circuit designers repeatedly synthesize and simulate circuits for debugging and incremental design, but due to the size of computational circuits these steps are slow and waste designer productivity. In this paper we present an architecture and tool flow for rapidly compiling and simulating/executing computational circuits. We use a motion estimation circuit to demonstrate the performance vs. capacity scalability of our architecture, and show that the performance is comparable to an FPGA-based design.

Self-hosted placement for massively parallel processor arrays

“…4. Architecture of a single PE from [3] In [7], the number of logic resources used in an FPGA to compute placement of a single cluster were much larger than the clusters themselves. In contrast, each PE in an MPPA is capable enough to handle placement of an element its own size.…”

“…Different approaches range from explicitly parallel programming models (such the approach used by Nethra/Ambric, in which numerous parallel programs are hand-coded in a Java-like language) and automatic synthesis and parallelization of code (e.g. [3], which synthesizes parallel programs from Verilog source code.) In most of these models, once the user program has been synthesized into a set of parallel processes, these processes must be placed and routed in a sequence analogous to traditional CAD flows for FPGAs.…”

“…Figs. 3 and 4 show the high-level and detailed MPPA described in [3]. This architecture consists of an array of identical processor elements (PEs) and a local routing fabric.…”

“…Each PE is a simple, 32-bit RISC-like core executing a program stored on local memory. Programs for each PE, as well as a static routing schedule for inter-PE communications, are synthesized [3] We propose a simulated annealing algorithm with the following characteristics:…”

Rapid Synthesis and Simulation of Computational Circuits in an MPPA

“…The RVEArch architecture, first presented in [2], is an array of processors that uses high-speed pipelined interconnect and time-multiplexing to achieve a softer capacity limit where capacity can be traded for performance. The key to accelerating simulation is more than just using additional processors; the low-latency, high-bandwidth NoC in many MPPAs is necessary to overcome the communication bot-tlenecks in traditional parallel simulators.…”