2013 23rd International Conference on Field Programmable Logic and Applications 2013
DOI: 10.1109/fpl.2013.6645505
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In pursuit of instant gratification for FPGA design

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Cited by 13 publications
(6 citation statements)
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“…TFlow [1], a turbo flow for modular FPGA design, aims to reduce the design compilation time. The motivating principle is to complete as much back-end computation as possible ahead of time, even if this makes module preparation more computationally expensive.…”
Section: Motivationmentioning
confidence: 99%
“…TFlow [1], a turbo flow for modular FPGA design, aims to reduce the design compilation time. The motivating principle is to complete as much back-end computation as possible ahead of time, even if this makes module preparation more computationally expensive.…”
Section: Motivationmentioning
confidence: 99%
“…Meanwhile, ARM-Linux kernel space can transfer data sampled by ADC in blocks to ARM-Linux user space (the maximum data block size is 120Kbytes), ARM can process data in ARM-Linux user space. [7] Real-time system must have ability to process and transmit data with high speed. In order to ensure constant and continuous data transmission, ARMLinux system uses ping-pong operation of two pieces of data buffer (the maximum data buffer size is 120K bytes) to achieve real-time data in series.…”
Section: Arm-linux Spi Bus Driver Designmentioning
confidence: 99%
“…In GReasy, an alternative method is used for bitstream generation. GReasy utilizes TFlow for back-end bitstream construction, which places and routes parameterized pre-compiled modules into a FPGA bitstream, and does so in a few seconds time -well within the expectation of a software-only flow [5].…”
Section: Introductionmentioning
confidence: 99%
“…TFlow is built on top of TORC which is an API for user manipulation of EDIF and XDL files as well as bitstream packets, and uses a library of pre-compiled modules and associated meta-data, enabling bitstream-level assembly of desired designs that can occur in a fraction of the time of traditional back-end tools [12], [5]. This is done by splitting the hardware design into two distinct phases.…”
Section: Introductionmentioning
confidence: 99%