Self-hosted placement for massively parallel processor arrays

Abstract

Abstract-We consider the placement problem as part of the CAD flow for a massively parallel processor arrays (MPPAs). In contrast to traditional placers, which operate on a workstation with one or several cores and are able to take advantage of parallelism to a limited degree, we investigate running the placer on the target architecture itself. As the number of processor elements (PEs) in such a device scale, so too does the computational power available to the placer. This natural scaling helps avoid the long runtimes that afflict FPGA flows.In this paper, we propose a distributed placer suitable to run on a MPPA. This placer takes advantage of local interconnect fabric, and may be efficiently coded on a simple, RISC-like core. We investigate the performance of this placer and compare it to traditional, simulated annealing-based placers using both unrealistic (but nearly optimal) and realistic (but suboptimal) annealing schedules.On a simulated 32 × 32 = 1024-core MPPA, the proposed algorithm furnishes placements within 5% of the optimal placement quality -a level competetive with the realistic, traditional placer. To do so, the distributed placer requires each PE to consider 1/256 th as many swaps as the traditional placer, a computational advantage which scales favourably as the number of cores on the MPPA increases.

Scalable and deterministic timing-driven parallel placement for FPGAs

“…More recently, work by Smecher, Wilton and Lemieux [38] demonstrated that the algorithm used in [37] could be applied to placement of communicating tasks for a Massively Parallel Processor Array (MPPA). Since MPPAs contain reasonably powerful CPUs, they can "self-host" or place themselves.…”

“…Smecher et al [38] to the full timing-driven placement algorithm from VPR 5.0 using Pthreads, allowing it to run on readily available shared-memory multicore computers.…”

Genesis

“…Casotto et al [1987] No Sequent Balance 8,000 (8-processors) 6.4× on 8 processors Kravitz and Rutenbar [1987] No VAX 11/784 (4-processors) 2.3× on 4 processors Rose et al [1988] No 6 Nat.Sem. 32,016 processors 4× with 5 processors Witte et al [1991] No Hypercube multiprocessors 8× with 16 processors Sun and Sechen [1994] No Networks of machines 3.3× on 16 processors Wrighton and Dehon [2003] No FPGAs 500×-2,500× over CPUs Ludwin et al [2008] Yes Multiprocessors 2.1× on 4 processors Smecher et al [2009] No MPPAs 1/256 less swaps with 1,024 cores Choong et al [2010] No GPU 10× on NVIDIA GTX280 Ludwin and Betz [2011] Yes Multiprocessors 2.4× on 8 processors Wang and Lemieux [2011] Yes Multiprocessors 161× using 25 processors…”

“…This leads to mentionable speedups; however, it is not widely accepted as it cannot follow the exponential growth in FPGA logic cell counts. -Develop novel parallel algorithms to take advantage of the existing and upcoming multicore processors [Casotto et al 1987;Choong et al 2010;Rose et al 1988;Ludwin et al 2008;Kravitz and Rutenbar 1987;Wrighton and Dehon 2003;Witte et al 1991;Smecher et al 2009]. With the current market trend of increasing the number of CPU cores rather than designing faster CPU cores [ITRS 2012], the usage of parallel CAD algorithms promises to alleviate the runtime crisis.…”