Scalable and deterministic timing-driven parallel placement for FPGAs

Abstract

This thesis describes a parallel implementation of the timing-driven VPR 5.0 simulated-annealing placement engine. By partitioning the grid into regions and allowing distant data to grow stale, it is possible to consider a large number of nonconflicting moves in parallel and achieve a deterministic result. The full timingdriven placement algorithm is parallelized, including swap evaluation, boundingbox calculation and the detailed timing-analysis updates. The partitioned region approach slightly degrades the placement quality, but this is necessary to expose greater parallelism. We also suggest a method to recover the lost quality.In simulated annealing, runtime can be shortened at the expense of quality.Using this method, the serial placer can achieve a maximum speedup of 100X while quality metrics degrades as much as 100%. In contrast, the parallel placer can scale beyond 500X with all quality metrics degrading by less than 30%. Specifically, at the point where the parallel placer begins to dominate over the serial placer, the post-routing minimum channel width, wirelength and critical-path delay degrades 13%, 10% and 7% respectively on average compared to VPR's original algorithm, while achieving a 140X to 200X speedup 25 threads. Finally, it is shown that the amount of degradation in the parallel placer is independent of the number of threads used.ii

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition

“…Modern processors contain multiple cores, and if these cores can operate together, the turn-around time of FPGA CAD iterations can be significantly shortened. There have been a number of papers from both industry and academia describing parallel CAD algorithms [5]- [13]. Each of these previous works describes how the problem space can be divided or decomposed into tasks for individual processors, and how strategic communication and synchronization can ensure acceptable quality of results.…”

“…Each of these previous works describes how the problem space can be divided or decomposed into tasks for individual processors, and how strategic communication and synchronization can ensure acceptable quality of results. In this paper, we enhance the timing-driven parallel placement algorithm described by Wang and Lemieux in [5]. Their solution divides the entire FPGA device into regions, each of which can be processed in parallel, and uses barriers to ensure that the overall result is deterministic.…”

“…In this paper, we consider two enhancements to the algorithm in [5]. First, we show that an improved decomposition strategy reduces the number of barriers required for synchronization, improving the overall run-time with the same quality of result (QoR).…”

“…First, we show that an improved decomposition strategy reduces the number of barriers required for synchronization, improving the overall run-time with the same quality of result (QoR). In [5], barriers are used to ensure that each processor sees a consistent view of the current solution; by being more aggressive in the manner in which processors share the optimization space, we can reduce the number of barriers while maintaining the deterministic nature of the original algorithm. We call the new approach the halfbox window decomposition method, or simply the half-box method for short.…”

“…Section II describes previous work, with an emphasis on the algorithm described in [5]. Section III shows how the number of barriers in the baseline algorithm can be reduced, and quantifies the impact on overall run-time.…”