A comprehensive approach for modeling the threshold voltage of nanoscale strained silicon-on-insulator (SSOI) and strained Si-on-SiGe-on-insulator (SSGOI) MOSFETs is presented. The model includes the effect of strain in terms of Ge mole fraction and various other device parameters-channel length, channel doping, strained silicon film thickness, gate oxide thickness and gate work function. The accuracy of the proposed threshold voltage model is verified using two-dimensional numerical simulations. We have also demonstrated that our model can accurately predict the DIBL effects.