A reliability methodology for low temperature data retention in floating gate non-volatile memories

Kuhn, P.; Hoefler, A.; Harp, T.; Hornung, B.; Paulsen, R.E.; Burnett, D.; Higman, J.M.

doi:10.1109/relphy.2001.922912

Cited by 15 publications

(4 citation statements)

References 11 publications

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“…From there, reliability extrapolations can be performed to estimate the number of failures. Other extrapolations procedures have been proposed, based on the same model or on empirical approximations [195][196][197][198][199][200][201][202][203], while addressing the optimization of the P/E waveforms and cell design [204][205][206][207]. Like all reliability issues, SILC becomes more of a concern in scaled MLCs or TLCs, because of the reduced separation between V T levels and smaller floating-gate capacitance, meaning that fewer electrons are stored into the floating gate and that even microscopic leakage currents can cause significant damage.…”

Section: Retention After Cycling and Silcmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Retention After Cycling and Silcmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…[4]. With the known interaction of the bitcell with the NVM design the end of life condition of the bitcells and the end of life failure rate can be accurately modeled.…”

Section: Floating Gate Nonvolatile Memoriesmentioning

confidence: 99%

Materials Challenges in Automotive Embedded Non-Volatile Memories

Prinz¹

2007

MRS Proc.

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Silicon-based nonvolatile memory modules are widely used in microcontrollers, where they are embedded into a monolithic system on a chip (SoC) which also includes high speed logic transistors, cache SRAM, and peripheral circuits for communicating with the external world. The physical principle most widely exploited for nonvolatile code and data storage is charge storage in floating gates. Charge storage in nitride traps, and more recently, in nanocrystals also has been explored.The most demanding use profiles with respect to temperatures, data retention times, and low failure rates are encountered in automotive engine control applications, where junction temperatures up to 150∞C are common, for 1000ís of hours. Starting with the 130nm technology node, embedded Flash technology has been integrated with copper interconnects, and at the 90nm node, low dielectric constant interlevel dielectrics are also employed to increase circuit performance. To achieve automotive reliability, the materials surrounding the silicon floating gate, nanocrystal, or nitride charge storage area must be evaluated for parasitic charge storage, write/erase stress-induced leakage current, and other parameters important for reliability. Any movement of parasitic charge, potentially over a long period of time, can reduce the sensing window of the Flash EEPROM bitcell.

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“…Traditionally data retention is addressed by means of high temperature bake, however, the activation energy of SILC is very low, this means that SILC related data retention study cannot be accelerated at elevated temperature [7,9]. One of the most effective methods to address SILC in NVM is to apply gate stress measurements [10,11].…”

Section: Silc In Random Accessible Non-volatile Memory Cell Arraysmentioning

confidence: 99%

Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

Tao

Scarpa

Marwijk

et al. 2004

Microelectronics Reliability

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A reliability methodology for low temperature data retention in floating gate non-volatile memories

Cited by 15 publications

References 11 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Materials Challenges in Automotive Embedded Non-Volatile Memories

Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

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