“…reducing tunnelling oxide thickness and using high-k dielectrics, without compromising on reliability and endurance, 3 as there are formidable challenges associated with physical scaling of devices, such as cell-to-cell interference, poor reliability and lower gate coupling ratio. [3][4][5][6][7][8] The use of charge trapping layers, encased in a high-k dielectric, 9,10 as storage nodes is the most promising route to overcome these issues. 8 Charge trapping devices, comprising of either interface traps or nanoparticles as storage nodes have been studied for a long time, [11][12][13] especially for military and space applications due to their enhanced radiation tolerance.…”