The statistical distribution of the natural threshold voltage (VT$ of 512k-bit NVM circuit arrays has been studied for two different technologies. The major source of the Vm variation is dopant fluctuations of the NVM well. An analytical model for the dopant fluctuations provides excellent agreement with the measured circuit VTO variation and NVM cell mismatch for both technologies.The reliability implications of the VTo variation are considered using charge leakage models for data retention.
A reliability assessment methodology consisting of a statistical model and experiments to evaluate the leakage mechanism responsible for Low Temperature Data Retention (LTDR) in floating gate non-volatile memories is presented. The nature of the leakage mechanism and the methodology necessary to observe and accurately assess this phenomenon are described.
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