A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC

Bunsen, Keigo; Martens, Ewout; Dermit, Davide; Craninckx, Jan

doi:10.1109/tcsii.2020.3046091

Cited by 3 publications

(2 citation statements)

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“…CMOS comparators are versatile components with wide-ranging applications in various electronic systems. Their ability to compare voltages accurately, provide precise outputs, and consume low power makes them essential for achieving high-performance, low-power designs in ADCs [1]- [5], DACs [6], [7], voltage references [8], overvoltage and undervoltage protection [9], motor control systems [10], [11], photovoltaic systems [12], [13], pulse-width modulation circuits, voltage level detection and window detection circuits. Comparators transform analog input signal differences into digital outputs.…”

Section: Introductionmentioning

confidence: 99%

A low power and high speed 45 nm CMOS dynamic comparator with low offset

Brindha,

Manjula

2023

IJPEDS

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<p><span lang="EN-US">The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sampling rate and accuracy of data converters. Moreover, addressing the offset voltage of comparators becomes crucial for achieving accurate signal conversion. To fulfill this need, a novel dynamic comparator has been designed, featuring high-speed operation, low-power consumption, and minimal offset. The circuit comprises a pre-amplifier with a charge pump, followed by a decision circuit and an output stage. Through simulations, the comparator has demonstrated low power consumption of 15.04 µW, a delay of 80.51 ps, and an extremely low offset voltage of 8 µV. These characteristics make it highly suitable for data converters. The comparator operates at a clock frequency of 1 GHz and a supply voltage of 1 V, and the simulation was conducted using the Cadence Virtuoso tool in a 45 nm CMOS technology.</span></p>

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Section: Introductionmentioning

confidence: 99%

A low power and high speed 45 nm CMOS dynamic comparator with low offset

Brindha,

Manjula

2023

IJPEDS

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“…Moreover, larger driving switches introduce more parasitic capacitance, which reduces the speed of the ADC. The redundancy can alleviate the settling error of a DAC [16][17][18][19][20][21][22][23][24][25][26][27][28]. The nonbinary redundancy [29] needs a complex digital control circuit and an extra an ROM.…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

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