A low power and high speed 45 nm CMOS dynamic comparator with low offset

Abstract

<p><span lang="EN-US">The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sampling rate and accuracy of data converters. Moreover, addressing the offset voltage of comparators becomes crucial for achieving accurate signal conversion. To fulfill this need, a novel dynamic comparator has been designed, featuring high-speed operation, low-power consumption, and minimal offset. The circuit comprises a pre-amplifier with a charge pump, followed by a decision circuit and an output stage. Through simulations, the comparator has demonstrated low power consumption of 15.04 µW, a delay of 80.51 ps, and an extremely low offset voltage of 8 µV. These characteristics make it highly suitable for data converters. The comparator operates at a clock frequency of 1 GHz and a supply voltage of 1 V, and the simulation was conducted using the Cadence Virtuoso tool in a 45 nm CMOS technology.</span></p>

Analysis of the parasitic capacitance effects on the layout of latch-based sense amplifiers for improving SRAM performance

“…Compared to static power consumption, dynamic power consumption has a significantly larger value and is the main component affecting the total power consumption of integrated circuit designs [1], [34]. Generally, passive power consumption is influenced by factors such as the operating voltage (VDD), the distributed total design capacitance (C), and the design operating frequency (f) [1], [33]. The power consumption and access time of a SA design can be improved by reducing its distributed total capacitance.…”