A practical approach of memory access parallelization to exploit multiple off-chip DDR memories

Kwon, Woocheol; Yoo, Sungjoo; Hong, Sun-Gi; Min, Byeong; Choi, Kyu-Myung; Eo, Soo-Kwan

doi:10.1145/1391469.1391585

Cited by 16 publications

(7 citation statements)

References 9 publications

(11 reference statements)

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“…Kwon et al proposed transaction ID renaming to perform dynamic reordering for concurrent accesses to multiple memories [Kwon et al 2008]. Ausavarungnirun et al target reducing the memory slowdown of the CPU without losing memory bandwidth in the GPU in GPGPU platforms [Ausavarungnirun et al 2012].…”

Section: Memory Schedulingmentioning

confidence: 99%

System-Level Performance and Power Optimization for MPSoC

Lin

Yang

Huang

et al. 2015

ACM Trans. Embed. Comput. Syst.

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As the number of IPs in a multimedia Multi-Processor System-on-Chip (MPSoC) continues to increase, concurrent memory accesses from different IPs increasingly stress memory systems, which presents both opportunities and challenges for future MPSoC design. The impact of such requirements on the system-level design for MPSoC is twofold. First, contention among IPs prolongs memory access time, which exacerbates the persisting memory wall problem. Second, longer memory accesses lead to longer IP stall time, which results in unnecessary leakage waste. In this article, we propose two memory access-aware system-level design approaches for performance and leakage optimization. To alleviate the memory wall problem, we propose a Hierarchical Memory Scheduling (HMS) policy that schedules memory requests from the same IP and application consecutively to reduce interference among memory accesses from different IPs with a fairness guarantee. To reduce IP leakage waste due to long memory access, we propose a memory accessaware power-gating policy. A straightforward power-gating approach is to power gate an IP when it needs to fetch data from memory. However, due to the response time variation among memory accesses, aggressively power gating an IP whenever a memory request occurs may result in incorrect power-gating decisions. The proposed memory access-aware power-gating policy makes these decisions judiciously, based on the predicted memory latency of an individual IP and its energy breakeven time. The experimental results show that the proposed HMS memory scheduling policy improves system throughput by 42% compared to First-Come-First-Serve (FCFS) and by 21% compared to First-Ready First-Come-First-Serve (FR-FCFS) on an MPSoC for mobile phones. For the improvement of fairness, HMS improves fairness by 1.52× compared to FCFS and by 1.23× compared to FRFCFS. In the aspect of leakage optimization, our memory accessaware power-gating mechanism improves energy savings by 3.88× and reduces the performance penalty by 70% compared to conventional timeout-based power gating. We further demonstrate that our HMS memory scheduler can regulate memory access orders, thereby reducing memory response time variation. This leads to more accurate power-down decisions for both conventional timeout power gating and the proposed memory access-aware power gating.

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Section: Memory Schedulingmentioning

confidence: 99%

System-Level Performance and Power Optimization for MPSoC

Lin

Yang

Huang

et al. 2015

ACM Trans. Embed. Comput. Syst.

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“…Reorder buffer is another approach. Kwon et al [8] proposed an idea of transaction id renaming and distributed soft arbitration in the context of multiple memories, with a reorder buffer in the network interface. However, it suffered from high area overhead and low utilization.…”

Section: Related Workmentioning

confidence: 99%

An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs

et al. 2014

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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Reorder buffers are often needed in multi-path routing networks-on-chips (NoCs) to guarantee in-order packet delivery. However, the buffer sizes are usually over-dimensioned, due to lack of worst-case analysis, leading to unnecessary larger area overhead. Based on network calculus, we propose an analysis framework for the worst-case reorder buffer size in multi-path minimal routing NoCs. Experiments with synthetic traffic and an industry case show that our method can effectively explore the traffic splitting space, as well as the mapping effects in terms of reorder buffer size with a maximum improvement of 36.50%.

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“…They present a concept of inter-memory controller arbitration where, in case of possible conflict at the destination, memory controllers select a winner to send data to the destination thereby avoiding such conflicts. In [24], the authors present a concept called transaction ID renaming (which is based on reorder buffers at network entry) in order to resolve a performance problem caused by the in-order requirements imposed on multiple traffic streams from one master to multiple memory channels. In [25], the authors improve the solution in [24] by removing the reorder buffer at network entry and, instead, exploiting buffer resources in network-on-chip for the reorder buffer purpose.…”

Section: Related Workmentioning

confidence: 99%

A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC

Kim

Yoo

Lee

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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3D stacked DRAM improves peak memory performance. However, its effective performance is often limited by the constraints of rowto-row activation delay (tRRD), four active bank window (tFAW), etc. In this paper, we present a quantitative analysis of the performance impact of such constraints. In order to resolve the problem, we propose balancing the budget of DRAM row activation across DRAM channels. In the proposed method, an inter-memory controller coordinator receives the current demand of row activation from memory controllers and re-distributes the budget to the memory controllers in order to improve DRAM performance. Experimental results show that sharing the budget of row activation between memory channels can give average 4.72% improvement in the utilization of 3D stacked DRAM.

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A practical approach of memory access parallelization to exploit multiple off-chip DDR memories

Cited by 16 publications

References 9 publications

System-Level Performance and Power Optimization for MPSoC

System-Level Performance and Power Optimization for MPSoC

An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs

A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC

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