Abstract:3D stacked DRAM improves peak memory performance. However, its effective performance is often limited by the constraints of rowto-row activation delay (tRRD), four active bank window (tFAW), etc. In this paper, we present a quantitative analysis of the performance impact of such constraints. In order to resolve the problem, we propose balancing the budget of DRAM row activation across DRAM channels. In the proposed method, an inter-memory controller coordinator receives the current demand of row activation fro… Show more
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