No abstract

Recent studies suggest that the intracoronary administration of bone marrow (BM)-derived mesenchymal stem cells (MSCs) may improve left ventricular function in patients with acute myocardial infarction (AMI). However, there is still argumentative for the safety and efficacy of MSCs in the AMI setting. We thus performed a randomized pilot study to investigate the safety and efficacy of MSCs in patients with AMI. Eighty patients with AMI after successful reperfusion therapy were randomly assigned and received an intracoronary administration of autologous BM-derived MSCs into the infarct related artery at 1 month. During follow-up period, 58 patients completed the trial. The primary endpoint was changes in left ventricular ejection fraction (LVEF) by single-photon emission computed tomography (SPECT) at 6 month. We also evaluated treatment-related adverse events. The absolute improvement in the LVEF by SPECT at 6 month was greater in the BM-derived MSCs group than in the control group (5.9%±8.5% vs 1.6%±7.0%; P=0.037). There was no treatment-related toxicity during intracoronary administration of MSCs. No significant adverse cardiovascular events occurred during follow-up. In conclusion, the intracoronary infusion of human BM-derived MSCs at 1 month is tolerable and safe with modest improvement in LVEF at 6-month follow-up by SPECT. (ClinicalTrials.gov registration number: NCT01392105)

This paper presents important, new results of a study on the problem of task scheduling and voltage allocation in dynamically variable voltage processors, the purpose of which was minimization of processor energy consumption. The contributions are twofold: (1) For given multiple discrete supply voltages and tasks with arbitrary arrival-time/deadline constraints, we propose a voltage allocation technique that produces a feasible task schedule with optimal processor energy consumption.(2) We then extend the problem to include the case in which tasks have nonuniform loads (i.e.; switched) capacitances and solve it optimally. The proposed technique, called Alloc-vt, in (1) is based on the prior results in [Yao, Demers and Shenker. 1995. In Proceedings of IEEE Symposium on Foundations of Computer Science. 374-382] (which is optimal for dynamically continuously variable voltages, but not for discrete ones) and [Ishihara and Yasuura. 1998. In Proceedings of International Symposium on Low Power Electronics and Design. 197-202] (which is optimal for a single task, but not for multiple tasks), whereas the proposed technique, called Alloc-vt cap , in (2) is based on an efficient linear programming (LP) formulation. Both techniques solve the allocation problems optimally in polynomial time.

In the many-core era, scalable coherence and on-chip interconnects are crucial for shared memory processors. While snoopy coherence is common in small multicore systems, directory-based coherence is the de facto choice for scalability to many cores, as snoopy relies on ordered interconnects which do not scale. However, directory-based coherence does not scale beyond tens of cores due to excessive directory area overhead or inaccurate sharer tracking. Prior techniques supporting ordering on arbitrary unordered networks are impractical for full multicore chip designs.We present SCORPIO, an ordered mesh Network-on-Chip (NoC) architecture with a separate fixed-latency, bufferless network to achieve distributed global ordering. Message delivery is decoupled from the ordering, allowing messages to arrive in any order and at any time, and still be correctly ordered. The architecture is designed to plug-and-play with existing multicore IP and with practicality, timing, area, and power as top concerns. Full-system 36 and 64-core simulations on SPLASH-2 and PARSEC benchmarks show an average application runtime reduction of 24.1% and 12.9%, in comparison to distributed directory and AMD HyperTransport coherence protocols, respectively.The SCORPIO architecture is incorporated in an 11 mm-by-13 mm chip prototype, fabricated in IBM 45nm SOI technology, comprising 36 Freescale e200 Power Architecture TM cores with private L1 and L2 caches interfacing with the NoC via ARM AMBA, along with two Cadence on-chip DDR2 controllers. The chip prototype achieves a post synthesis operating frequency of 1 GHz (833 MHz post-layout) with an estimated power of 28.8 W (768 mW per tile), while the network consumes only 10% of tile area and 19 % of tile power.

This paper presents a set of new important results for the problem of task scheduling and voltage allocation in dynamically variable voltage processor for minimizing the total processor energy consumption. The contributions are two folds: (1) For given multiple discrete supply voltages and tasks with arbitrary arrival-time/deadline constraints, we propose a voltage allocation technique which produces a feasible task schedule with optimal processor energy consumption; (2) We then extend the problem to include the case in which tasks have non-uniform load (i.e., switched) capacitances, and solve it optimally.

No abstract

Only a small proportion of the ventricle is subjected to external chest compression when CPR is performed according to the current guidelines. Compression of the sternum at the sternoxiphoid junction might be more effective to compress the ventricles.

In patients who underwent primary PCI for STEMI, an increased IMR has an independent predictive value for MVO detection, and combined high IMR and low CFRthermo are highly predictive of MVO. These indexes could be used to further risk-stratify patients and guide regional and systemic therapies.