A Potential Model for Parallel Gated Junctionless Field Effect Transistor

Raibaruah, Apurba Kumar; Sarma, Kaushik Chandra Deva

doi:10.1007/s12633-020-00890-8

Cited by 7 publications

(2 citation statements)

References 22 publications

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“…In the temperature range of 298-398 K, the effect of temperature on various electric parameters like SS, threshold voltage was studied. Also, an analytical model for the centre longitudinal potential 63 using boundary conditions at the intersections of adjacent sections had been developed by them. The resultant model is compared to simulation results from TCAD.…”

Section: A Review On Different Types Of Modeling Of Junctionless Fet ...mentioning

confidence: 99%

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Raut¹,

Nanda²,

Panda³

2023

ECS J. Solid State Sci. Technol.

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Junction-less field effect transistors, also known as JLFETs, are widely regarded as the most promising candidate to replace the conventional metal oxide semiconductor field effect transistors (MOSFETs) currently used in integrated circuit technology. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold slope and drain induced barrier lowering (DIBL). Due to its gate coupling, the gate-all-around (GAA) JLFET is a better contender to uphold Moore's law than other existing device architectures and regular JLFET, allowing more precise channel tuning. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, no comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters have been provided in a single resource. From device evaluation and application to qualitative and quantitative parameter analysis studies likewise subthreshold swing, DIBL and switching ratio, this review provides comprehensive information on the various structures of Junctionless and GAA JLFETs. Furthermore, various device modeling techniques of JLFETs for enhancing the device's characteristics and its application in various semiconductor industries are provided.

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Section: A Review On Different Types Of Modeling Of Junctionless Fet ...mentioning

confidence: 99%

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Raut¹,

Nanda²,

Panda³

2023

ECS J. Solid State Sci. Technol.

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“…It has now become a rising device in the non-volatile memory market. In this work, we are going to carry out the modeling of the depletion layer and threshold voltage of the Parallel Gated Junctionless FET (PGJLFET) [17,18]. PGJLFET works better during the ON state as compared to conventional Junctionless Transistors [17].…”

Section: Introductionmentioning

confidence: 99%

An Analytical Model for the Depletion Region Width and Threshold Voltage of a Parallel Gated Junctionless Field Effect Transistor

Raibaruah¹,

Sarma²

2022

J. Nano- Electron. Phys.

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This paper reports on the modeling of the depletion region width and threshold voltage of a parallel gated junctionless field effect transistor. The depletion region width is obtained by resolving 1D Poisson equation along the channel of the device in the y-direction. The central potential through the channel region of the device is also considered. With the help of the depletion region width and device central potential model, the threshold voltage of the device is obtained. Exploration has been made for different variations of the depletion width depending on the gate to source voltage, gate oxide thickness, and different gate dielectric materials. For a 0.6 V gate bias, a 4 nm depletion width is achieved. The threshold voltage variation is obtained and analyzed by considering different drain voltages, doping concentrations, temperatures, and work functions. The device at 10 19 cm -3 doping concentration, 300 K temperature, and 5.4 eV work function with a drain voltage of 1 V allows a threshold voltage of 0.47 V.

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Performance Analysis of 3-D Parallel Gated Junctionless Field Effect Nanowire Transistor

Bora,

Sureka,

Deka

et al. 2022

Intelligent Computing Techniques for Smart Energy Systems

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A Potential Model for Parallel Gated Junctionless Field Effect Transistor

Cited by 7 publications

References 22 publications

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

An Analytical Model for the Depletion Region Width and Threshold Voltage of a Parallel Gated Junctionless Field Effect Transistor

Performance Analysis of 3-D Parallel Gated Junctionless Field Effect Nanowire Transistor

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