An Analytical Model for the Depletion Region Width and Threshold Voltage of a Parallel Gated Junctionless Field Effect Transistor

Abstract

This paper reports on the modeling of the depletion region width and threshold voltage of a parallel gated junctionless field effect transistor. The depletion region width is obtained by resolving 1D Poisson equation along the channel of the device in the y-direction. The central potential through the channel region of the device is also considered. With the help of the depletion region width and device central potential model, the threshold voltage of the device is obtained. Exploration has been made for different variations of the depletion width depending on the gate to source voltage, gate oxide thickness, and different gate dielectric materials. For a 0.6 V gate bias, a 4 nm depletion width is achieved. The threshold voltage variation is obtained and analyzed by considering different drain voltages, doping concentrations, temperatures, and work functions. The device at 10 19 cm -3 doping concentration, 300 K temperature, and 5.4 eV work function with a drain voltage of 1 V allows a threshold voltage of 0.47 V.