A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance

Narendar, Vadthiya; Narware, Pallavi; Bheemudu, V.; Bhukya, Sunitha

doi:10.1016/j.aeue.2020.153459

Cited by 17 publications

(10 citation statements)

References 38 publications

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“…Low power dissipation and more speed in SRAM is obtained by using advanced devices such as FinFET instead of MOSFET. To meet technology scaling new structure challenges have been proposed such as FinFET and Nanowire [13]. FinFET device attracted many SRAM designer's as FinFET has superior short channel effects, reduced dopant uctuations, independent gating, better subthreshold slope [13,14].…”

Section: Static Random Access Memory (Sram)mentioning

confidence: 99%

“…To meet technology scaling new structure challenges have been proposed such as FinFET and Nanowire [13]. FinFET device attracted many SRAM designer's as FinFET has superior short channel effects, reduced dopant uctuations, independent gating, better subthreshold slope [13,14]. From device level to architecture level many FinFET based SRAM cells have been proposed [15][16][17]…”

Section: Static Random Access Memory (Sram)mentioning

confidence: 99%

“…Due to continuous scaling FinFET faces several challenges in terms of cost effective, patterning, layout, device performance [9][10][11][12]. Due to several advantages FinFET can be used in variety of application such as terrestrial systems, infrared detectors, space, satellite communication, nuclear reactor, military [12][13].…”

Section: Introductionmentioning

confidence: 99%

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Reliability and Power Analysis of FinFET Based SRAM

Navaneetha¹,

Bikshalu

2021

Silicon

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Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as nonplanar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed.Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM les in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.

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Section: Static Random Access Memory (Sram)mentioning

confidence: 99%

Section: Static Random Access Memory (Sram)mentioning

confidence: 99%

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Reliability and Power Analysis of FinFET Based SRAM

Navaneetha¹,

Bikshalu

2021

Silicon

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“…Different dielectric spacers with different proportion and con gurations can be used for better device characteristics as compared to the conventional FET [14][15][16][17]. Recently, the signi cant reduction in power has been examined in performance of JLT has been improved using spacer engineering.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length

Kaur

Gill

Kaur

2022

Silicon

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In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (I ON ), off-current (I OFF ), subthreshold swing (SS), drain induced barrier lowering (DIBL), transconductance (g m ), transconductance generation factor (TGF), output conductance (g d ), early voltage (V ea ) and intrinsic gain (A v ). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device. Parameters κ=15Source side Both sides Drain side

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“…The addition of BSP to the fin changes the active fin height and hence the effective channel width is modulated giving better SS, DIBL, and improved performance of the device. Later Narendar et al, 25,26 demonstrated the BSP Ground plane (GP) FinFET with dual material gate engineering and obtained optimized performance.…”

mentioning

confidence: 99%

Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

Valasa¹,

Kotha²,

Narendar³

et al. 2023

ECS J. Solid State Sci. Technol.

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This article for the first time reports the design and performance optimization of Junctionless (JL) Bottom spacer (BSP) FinFET. Initially to get the desired value of workfunction (∅_m) and fin thickness (Tfin) for analog/RF analysis, the optimization of these parameters has been done by considering several values. It has been noticed that the increase in ∅_m and reduction in Tfin can lead to better electrical performance with suppressed short channel effects (SCE). Further, it is also observed that reduction in bottom spacer height (HBSP) can fetch enhanced analog/RF performance considering the improvement noticed in transconductance (gm), intrinsic gain (AV), transconductance generation factor (TGF), cutoff frequency (fT), and Gain frequency product (GFP). Moreover, when the bottom spacer dielectric permittivity (KBSP) is increased from 3.9 to 22, it has been found that the analog/RF performance degrades significantly.

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A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance

Cited by 17 publications

References 38 publications

Reliability and Power Analysis of FinFET Based SRAM

Reliability and Power Analysis of FinFET Based SRAM

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length

Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

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