Reliability and Power Analysis of FinFET Based SRAM

Navaneetha, Alluri; Bikshalu, Kalagadda

doi:10.1007/s12633-021-01345-4

Cited by 5 publications

(5 citation statements)

References 25 publications

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“…For the on-state current density, Figure 2a shows two defect clusters with 54 defects: the rectangular defect cluster 6 × 3.75 × 2 nm 3 and square defect cluster 3 × 3.75 × 3 nm 3 . Figure 2b shows the off-state current density of the fin.…”

Section: Resultsmentioning

confidence: 99%

“…Static random access memory (SRAM) is used as CPU cache memory, occupying over half of the System-on-Chip (SoC) die area. The high density of SRAM with nanosized transistors is vulnerable to variability due to process variations and short-channel effects such as drain-induced barrier lowering (DIBL), non-ideal subthreshold swing ( SS ), and threshold voltage (V th ) roll-off [ 1 , 2 , 3 , 4 ]. The fin field-effect transistor (FinFET)-based SRAM has been adopted to overcome the problems of planar SRAM [ 5 ].…”

Section: Introductionmentioning

confidence: 99%

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Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects

Bang

Lee

et al. 2023

Micromachines

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We comprehensively investigate displacement-defect-induced current and static noise margin variations in six-transistor (6T) static random access memory (SRAM) based on a 10 nm node fin field-effect transistor (FinFET) using technology computer-aided design (TCAD). Various defect cluster conditions and fin structures are considered as variables to estimate the worst-case scenario for displacement defects. The rectangular defect clusters capture more widely distributed charges at the fin top, reducing the on- and off-current. The read static noise margin (RSNM) is the most degraded in the pull-down transistor during the read operation. The increased fin width decreases the RSNM due to the gate field. The current per cross-sectional area increases when the fin height decreases, but the energy barrier lowering by the gate field is similar. Therefore, the reduced fin width and increased fin height structure suit the 10 nm node FinFET 6T SRAMs with high radiation hardness.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects

Bang

Lee

et al. 2023

Micromachines

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“…Navaneetha and Bikshalu [27] state that the VLSI industry requires anticipating tolerance of variability to ensure optimized performance of FinFET circuits. In this research, the Cadence Virtuoso tool is used to investigate the impact of fuctuations in voltage and temperature on 7 nm FinFETbased circuits.…”

Section: Related Workmentioning

confidence: 99%

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Rao¹,

Mamidipaka²,

Raghutu³

et al. 2023

Journal of Electrical and Computer Engineering

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Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

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“…In order to improve performance with a lower leakage current, the high-k dielectric medium which includes silicon nitrate and hafnium dioxide is employed in the proposed n-MOSFET. 7 In recent years, memories have come to be regarded as the key element in the structure of memory in computing systems.…”

mentioning

confidence: 99%

Design and Simulation of Bi-Layer Optimized High K- Dielectric Medium for N-Mosfet with Wild Horse Optimization to Improve Electrical Characteristics

Pavithra Guru

2024

ECS J. Solid State Sci. Technol.

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Electronic devices for advanced modern semiconductor based technology, mainly focus on the design regarding lighter, faster and more affordable solutions to meet the specifications of modern digital electronics. Some of the drawbacks for minimizing device size in MOSFET include gate insulator scaling, Short-Channel Effects (SCEs), shallow junction technology and off-state leakage current in MOSFET devices. In addition, the traditional SiO2 as a dielectric material contains restricted maximum capacitance as well as increased tunnel current leakage due to the thickness. Hence, a High-k dielectric is required to replace SiO2 to overcome the mentioned issues. In this model, the N-type MOSFET is designed based on the bi-layer high K-dielectric medium with optimized thickness according to the maximum capacitance and minimum threshold voltage, which are implemented on VLSI based applications such as 6 T SRAM for evaluating the performance. The drain current of HfO2, Al2O3 and HfO2+Si3N4 for 2.5 v drain voltage are 1.87 mA, 1.51 mA and 3.54 mA. Then, the read and write delay of the single and bi-layer MOSFET are 70.84 ps, 82.64 ps, 95.21 ps and 10.24 ps, 15.47 ps, 21.74 ps. Thus, the designed and simulated bi-layer optimized high k- dielectric medium for N-MOSFET with wild horse optimization performs better electrical characteristics than the single layer dielectric medium MOSFET.

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Reliability and Power Analysis of FinFET Based SRAM

Cited by 5 publications

References 25 publications

Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects

Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Design and Simulation of Bi-Layer Optimized High K- Dielectric Medium for N-Mosfet with Wild Horse Optimization to Improve Electrical Characteristics

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