A New Cell-to-Cell Interference Induced by Conduction Band Distortion near S/D Region in Scaled NAND Flash Memories

Abstract

A new cell-to-cell interference phenomenon has been found beyond sub 40nm node. Unlike capacitive coupling between floating gates, the threshold voltage (V TH ) shift of interfered cell becomes significantly large beyond some V TH of interfering cell. This is due to conduction band distortion near source and drain regions. In NAND Flash, drain and source are not biased directly but influenced by adjacent floating gate (FG) potential in small dimension. We named this new phenomenon Floating-gate Induced Barrier enhancement (FIBE). The model is confirmed by experiment and simulation. To reduce FIBE, asymmetric S/D junction structure and the bias scheme by using variable read voltage are suggested.

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory

“…From a reliability perspective, joint-DMYs will skip the program and erase the operation. However, joint-DMYs may still suffer disturbance during erase operation and further lead to adjacent WL interference effects [6][7][8]. In this work, the phenomenon of joint-DMYs Vt shift during erase cycling is reported, and it found that the backward electron injection during erase cycling is responsible for the joint-DMYs Vt shift.…”

A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

“…In effect, the channel of the main cells is based on the ultra-thin body (UTB) structure, which is not connected to the substrate [15,16]. Therefore, during the read operation, the selected cell is affected by the V read (read voltage) of the adjacent cell, which leads to cell-to-cell interference [11,12,17]. Since the cell-to-cell interference is different from the conventional FG (floating gate) of a planar 2D NAND structure [18][19][20], research on the cell-to-cell interference in 3D NAND has not been investigated yet.…”