A new cell-to-cell interference phenomenon has been found beyond sub 40nm node. Unlike capacitive coupling between floating gates, the threshold voltage (V TH ) shift of interfered cell becomes significantly large beyond some V TH of interfering cell. This is due to conduction band distortion near source and drain regions. In NAND Flash, drain and source are not biased directly but influenced by adjacent floating gate (FG) potential in small dimension. We named this new phenomenon Floating-gate Induced Barrier enhancement (FIBE). The model is confirmed by experiment and simulation. To reduce FIBE, asymmetric S/D junction structure and the bias scheme by using variable read voltage are suggested.
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