A multifunctional high-speed switch element for ATM applications

Hofmann, Ralf; Muller, R.

doi:10.1109/4.142599

Cited by 18 publications

(1 citation statement)

References 3 publications

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“…The average board-level interconnection length (in units of chip pitches) is (11) where is Rent's constant, estimated for this application. With an estimated fan-out , number of board wiring layers , wiring efficiency , and wiring pitch m, we can find the average chip footprint as (12) from which we can find the worst case board trace length (13) The capacitance associated with a minimum-sized transistor can be estimated (in femtofarads) as (14) Given the results of (9)- (14), with an estimated channel resistance for a minimum sized PMOS transistor in saturation k (roughly independent of technology), pad capacitance pF, package output impedance , intrinsic wiring resistance /cm, intrinsic wiring capacitance pF/cm, and transport velocity cm/ns, we can determine the worst case chip-to-chip delay (15) where is the number of stages required in the output pad driver, and is given by (16)…”

Section: B Pin Speed Limitsmentioning

confidence: 99%

Physical performance limits for shared buffer ATM switches

Schultz

Gulak

1997

IEEE Trans. Commun.

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Performance studies, linking ATM switch capabilities to physical limitations imposed by integrated circuit technology, have been scarce. This paper explores trends in circuit capabilities, and makes projections toward the 0.25-m technologies that will be available to all switch designers in the year 2000. The limits imposed by circuit technology are applied to shared buffer ATM switches. We determine requirements and physical limits for buffer capacity, buffer throughput, chip I/O throughput, and power dissipation. As a result, we are able to project chip counts, aggregate switch throughputs, and switch dimensions. As well, performance capabilities of singlechip shared buffer switches are estimated. A single-chip shared buffer switch implemented in 0.25-m technology will be capable of an aggregate throughput of 1.3 Tb/s, will accomplish almost arbitrarily low cell loss rates for bursty traffic, and may be integrated together with translation tables supporting hundreds of connections per port.

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